X28C512_06 Datasheet, PDF(15/21 Page) Intersil Corporation

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X28C512_06 Datasheet, PDF (15/21 Pages) Intersil Corporation – 5V, Byte Alterable EEPROM

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CE Controlled Write Cycle

Address

Data In

tAS

tOES

tCS

tDV

Data Out

Page Write Cycle

X28C512, X28C513

tAH

tCW

tWC

tWPH

tOEH

tCH

Data Valid

tDS

tDH

HIGH Z

(Note 5)

Address*

(Note 6)

tWP

tBLC

tWPH

I/O

Last Byte

Byte 0

Byte 1

Byte 2

Byte n

Byte n+1

*For each successive write within the page write operation, A7-A15 should be the same or

writes to an unknown address could occur.

Byte n+2

tWC

NOTES:

5. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch

data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.

6. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the

CE or WE controlled write cycle timing.

FN8106.2

June 7, 2006

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