X28C512_06 Datasheet, PDF (14/21 Pages) Intersil Corporation – 5V, Byte Alterable EEPROM

X28C512, X28C513
Write Cycle Limits
SYMBOL
PARAMETER
t_WC (Note 4)
t_AS
t_AH
t_CS
t_CH
t_CW
t_OES
t_OEH
t_WP
t_WPH
t_DV
t_DS
t_DH
t_DW
t_BLC
Write cycle time
Address setup time
Address hold time
Write setup time
Write hold time
CE pulse width
OE HIGH setup time
OE HIGH hold time
WE pulse width
WE High recovery
Data valid
Data setup
Data hold
Delay to next write
Byte load cycle
WE Controlled Write Cycle
Address
CE
t_AS
t_AH
t_CS
MIN
0
50
0
0
100
10
10
100
100
50
0
10
0.2
t_WC
t_CH
MAX
10
1
100
UNIT
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
µs
OE
t_OES
t_OEH
t_WP
WE
t_DV
Data In
Data Out
Data Valid
t_DS
t_DH
HIGH Z
NOTE:
4. t_WC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device
requires to complete the internal write operation.
14
FN8106.2
June 7, 2006