ISL75052SEH Datasheet, PDF (8/16 Pages) Intersil Corporation – 1.5A, Rad Hard, Positive, High Voltage LDO

ISL75052SEH
pin and GND. If the short or overload condition is removed from
V_OUT, then the output returns to normal voltage mode regulation.
In the event of an overload condition the LDO will begin to cycle
on and off due to the die temperature exceeding thermal fault
condition. However, one may never witness thermal cycling if the
heatsink used for the package can keep the die temperature
below the limits specified for thermal shutdown. The ROCP can
be calculated using the equation:
R_OCP = 893 ⁄ I_OCP
(EQ. 1)
Where:
R_OCP = The OCP resistor value in ohms.
I_OCP = The required OCP threshold in amps.
ESD Clamps
The ESD_CL_12V ESD clamps break down at nominally 17V. The
ESD_RC_7V clamps break down at nominally 7.5V with a
tolerance of ±10%. The PG pin has a diode to GND. The VOUT pin
has a diode to VIN (see “Pin Descriptions” on page 3).
COMP Pin
This pin helps compensate the device for various load conditions.
For 4.0V < VIN < 6.0V use RCOMP = 40k and CCOMP = 1nF. For
6V < VIN < 13.2V use RCOMP = 40k and CCOMP = 4.7nF. The
max current of the COMP pin when shorted to GND is 160µA.
Undervoltage Lockout
The undervoltage lockout function detects when VCCX exceeds
3.2V. When that level is reached, the LDO feedback loop is
closed and the LDO can begin regulating. This is achieved by
freeing the BYP net to charge up and act as a reference voltage
to the EA. Prior to that happening, the LDO Power PMOS device is
clamped off.
Bottom Metal Electrical Potential
The package bottom metal is electrically isolated and unbiased.
The bottom metal may be electrically connected to any potential
which offers the best thermal path through conductive mounting
materials (conductive epoxy, solder, etc.) or may be left unbiased
through the use of electrically non-conductive mounting
materials (non-conductive epoxy, Sil-pad, kapton film, etc.).
Bottom Metal Mounting Guidelines
The package bottom is a solderable metal surface. The following
JESD51-5 guidelines may be used to mount the package:
• Place a thermal land on the PCB under the bottom metal.
• The land should be approximately the same size to 1mm
larger than the 0.19x0.41inch bottom metal.
• Place an array of thermal vias below the thermal land.
• Via array size: ~4 x 9 = 36 thermal vias
• Via diameter: ~0.3mm drill diameter with plated copper on
the inside of each via.
• Via pitch: ~1.2mm.
Vias should drop to and contact as much buried metal area as
feasible to provide the best thermal path.
Thermal Fault Protection
In the event the die temperature exceeds +170°C (typ.) the
output of the LDO will shut down until the die temperature can
cool down to +150°C (typ.). The level of power combined with the
thermal impedance of the package (θ_JC of 5°C/W for the 16 Ld
CDFP package) will determine if the junction temperature
exceeds the thermal shutdown temperature specified in the
specification table (see “Bottom Metal Mounting Guidelines” on
page 8).
8
FN8456.0
May 29, 2013