ISL75052SEH Datasheet, PDF (3/16 Pages) Intersil Corporation – 1.5A, Rad Hard, Positive, High Voltage LDO

Pin Configuration
VOUT
VOUT
VIN
VIN
VIN
NC
NC
OCP
ISL75052SEH
ISL75052SEH
(16 Ld CDFP)
TOP VIEW
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
BYP
ADJ
EN
GND
COMP
TMODE
PG
VCCX
DOTTED LINE SHOWS METAL BOTTOM
Pin Descriptions
PIN NUMBER
3, 4, 5
10
13
9
1, 2
12
15
6, 7
16
8
14
11
PIN NAME
VIN
PG
GND
VCCX
VOUT
COMP
ADJ
NC
BYP
OCP
EN
TMODE
Bottom
Metallization
DESCRIPTION
ESD CIRCUIT
Input supply pins.
Circuit 1
This pin is logic high when V_OUT is in regulation signal. A logic low defines when V_OUT Circuit 2
is not in regulation.
GND pin. Pin 13 is also connected to the metal lid of the package.
Circuit 2
The 3.8V internal bus is pinned out to accept a decoupling capacitor. Connect a 0.1µF Circuit 2
ceramic capacitor from VCCX pin to GND.
Output voltage pins.
Circuit 1
Add compensation capacitor & resistor between COMP and GND.
Circuit 2
ADJ pin allows V_OUT to be programmed with an external resistor divider.
No connect. May be grounded if needed.
Circuit 2
Circuit 2
Connect a 0.1µF capacitor from BYP pin to GND, to filter the internal VREF.
Circuit 2
OCP pin allows the Current limit to be programmed with an external resistor.
Circuit 2
V_IN independent chip enable. TTL and CMOS compatible.
Test Mode pin, must be connected to GND.
Circuit 2
Circuit 2
The metal surface on the bottom surface of the package is floating. For mounting
instructions see “Bottom Metal Mounting Guidelines” on page 8.
Circuit 2
PAD
PAD
ESD_CL_12V
GND
ESD CIRCUIT 1
ESD_RC_7V
GND
ESD CIRCUIT 2
3
FN8456.0
May 29, 2013