ISL6567 Datasheet, PDF (8/26 Pages) Intersil Corporation – Multipurpose Two-Phase Buck PWM Controller with Integrated MOSFET Drivers

ISL6567
For more information, refer to “External Reference
Operation” on page 14.
EN (Pin 9)
This pin is a precision-threshold (approximately 0.6V) enable
pin. Pulled above the threshold, the pin enables the controller
for operation, initiating a soft-start. Normally a high impedance
input, once it is pulled above its threshold, a small current is
sourced on this pin; this current, along with a properly sized
resistor network, allows the user to adjust the threshold
hysteresis. Pulled below the falling threshold, this pin disables
controller operation, by ramping down the SS voltage and
discharging the output.
RGND, VSEN, and VDIFF (Pins 1, 2, and 4)
The inputs and output of the on-board unity-gain operational
amplifier intended for differential output sensing. Connect
RGND and VSEN to the output load’s local GND and VOUT,
respectively; VDIFF will reflect the load voltage referenced to
the chip’s local ground. Connect the feedback network to the
voltage thus reflected at the VDIFF pin. Should the circuit not
allow implementation of remote sensing, connect the VSEN
and RGND pins to the physical place where voltage is to be
regulated.
Connect the resistor divider setting the output voltage at the
input of the differential amplifier. To minimize the error
introduced by the resistance of differential amplifier’s inputs,
select resistor divider values smaller than 1kΩ. VDIFF is
monitored for overvoltage events and for PGOOD reporting
purposes.
FB and COMP (Pins 5 and 6)
The internal error amplifier’s inverting input and output
respectively. These pins are connected to the external
network used to compensate the regulator’s feedback loop.
ISEN1, ISEN2 (Pins 17, 13)
These pins are used to close the current feedback loop and
set the overcurrent protection threshold. A resistor
connected between each of these pins and their
corresponding PHASE pins determine a certain current flow
magnitude during the lower MOSFET’s conduction interval.
The resulting currents established through these resistors
are used for channel current balancing and overcurrent
protection.
Use Equation 1 to select the proper R_ISEN resistor:
R_ISEN
=
r_{---D----S----(--O----N-----)---}×_-----I_{--O----U----T--}
50 μ A
(EQ. 1)
where:
r_DS(ON) = lower MOSFET drain-source ON-resistance (Ω)
I_OUT = channel maximum output current (A)
Read “Current Loop” page 10, “Channel-Current Balance”
page 11, and “Overcurrent Protection” on page 12 for more
information.
UGATE1, UGATE2 (Pins 19, 11)
Connect these pins to the upper MOSFETs’ gates. These
pins are used to control the upper MOSFETs and are
monitored for shoot-through prevention purposes. Minimize
the impedance of these connections. Maximum individual
channel duty cycle is limited to 66%.
BOOT1, BOOT2 (Pins 20, 10)
These pins provide the bias voltage for the upper MOSFETs’
drives. Connect these pins to appropriately-chosen external
bootstrap capacitors. Internal bootstrap diodes connected to
the PVCC pins provide the necessary bootstrap charge.
Minimize the impedance of these connections.
PHASE1, PHASE2 (Pins 18, 12)
Connect these pins to the sources of the upper MOSFETs.
These pins are the return path for the upper MOSFETs’
drives. Minimize the impedance of these connections.
LGATE1, LGATE2 (Pins 16, 14)
These pins are used to control the lower MOSFETs and are
monitored for shoot-through prevention purposes. Connect
these pins to the lower MOSFETs’ gates. Minimize the
impedance of these connections.
SS (Pin 23)
This pin allows adjustment of the output voltage soft-start
ramp rate, as well as the hiccup interval following an
overcurrent event. The potential at this pin is used as a clamp
voltage for the internal error amplifier’s non-inverting input,
regulating its rate of rise during start-up. Connect this pin to a
capacitor referenced to ground. Small internal current sources
linearly charge and discharge this capacitor, leading to similar
variation in the ramp up/down of the output voltage. While
below 0.3V, all output drives are turned off. As this pin ramps
up, the drives are not enabled but only after the first UGATE
pulse emerges (avoid draining the output, if pre-charged). If
no UGATE pulse are generated until the SS exceeds the top
of the oscillator ramp, at that time all gate operation is
enabled, allowing immediate draining of the output, as
necessary.
SS voltage has a ~0.7V offset above the reference clamp,
meaning the reference clamp rises from 0V with unity gain
correspondence as the SS pin exceeds 0.7V. For more
information, please refer to “Soft-Start” on page 11.
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FN9243.3
May 28, 2009