ISL6567 Datasheet, PDF (23/26 Pages) Intersil Corporation – Multipurpose Two-Phase Buck PWM Controller with Integrated MOSFET Drivers

ISL6567
Size the trace interconnects commensurate with the signals
they are carrying. Use narrow (0.005” to 0.008”) and short
traces for the high-impedance, small-signal connections, such
as the feedback, compensation, soft-start, frequency set,
enable, reference track, etc. The wiring traces from the IC to
the MOSFETs’ gates and sources should be wide (0.02” to
0.05”) and short, encircling the smallest area possible.
Component Selection Guidelines
MOSFETS
The selection of MOSFETs revolves closely around the
current each MOSFET is required to conduct, the switching
characteristics, the capability of the devices to dissipate heat,
as well as the characteristics of available heat sinking. Since
the ISL6567 drives the MOSFETs with a 5V signal, the
selection of appropriate MOSFETs should be done by
comparing and evaluating their characteristics at this specific
V_GS bias voltage. The following paragraphs addressing
MOSFET power dissipation ignore the driving losses
associated with the gate resistance.
The aggressive design of the shoot-through protection
circuits, part of the ISL6567 output drivers, is geared toward
reducing the deadtime between the conduction of the upper
and the lower MOSFET/s. The short deadtimes, coupled with
strong pull-up and pull-down output devices driving the
UGATE and LGATE pins make the ISL6567 best suited to
driving low gate resistance (R_G), late-generation MOSFETs. If
employing MOSFETs with a nominal gate resistance in
excess of 1-2Ω, check for the circuit’s proper operation. A few
examples (non exclusive list) of suitable MOSFETs to be used
in ISL6567 applications include the D8 (and later) generation
from Renesas and the OptiMOS®2 line from Infineon. Along
the same line, the use of gate resistors is discouraged, as
they may interfere with the circuits just mentioned.
LOWER MOSFET POWER CALCULATION
Since virtually all of the heat loss in the lower MOSFET is
conduction loss (due to current conducted through the channel
resistance, r_DS(ON)), a quick approximation for heat dissipated
in the lower MOSFET can be found using Equation 25:
P_LMOS1
=
r_DS(ON)
⎛
⎜
⎝
-^I-^O-----^U----^T--⎟⎞
2⎠
2
(1
–
D)
+
-^I-^L----^,-^P----^P2----⁽--¹-----–-----^D-----⁾
12
(EQ. 25)
where: I_M is the maximum continuous output current, I_L,PP is
the peak-to-peak inductor current, and D is the duty cycle
(approximately V_OUT/V_IN).
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I_M, V_D(ON); the switching
frequency, f_S; and the length of dead times, t_d1 and t_d2, at
the beginning and the end of the lower-MOSFET conduction
interval, respectively.
P_{LMOS 2}
=
V_D(ON) f_S
⎛
⎜
-^I-^O-----^U----^T--
⎝2
+
I_{--P----P--⎟⎞}
2⎠
t_d1
+
⎛
⎜
-^I-^O-----^U----^T--
⎝2
–
I_{--P----P--⎟⎞}
2⎠
t_d2
(EQ. 26)
Equation 26 assumes the current through the lower
MOSFET is always positive; if so, the total power dissipated
in each lower MOSFET is approximated by the summation of
P_LMOS1 and P_LMOS2.
UPPER MOSFET POWER CALCULATION
In addition to r_DS(ON) losses, a large portion of the
upper-MOSFET losses are switching losses, due to currents
conducted through the device while the input voltage is
present as V_DS. Upper MOSFET losses can be divided into
separate components, separating the upper-MOSFET
switching losses, the lower-MOSFET body diode reverse
recovery charge loss, and the upper MOSFET r_DS(ON)
conduction loss.
In most typical circuits, when the upper MOSFET turns off, it
continues to conduct a decreasing fraction of the output
inductor current as the voltage at the phase node falls below
ground. Once the lower MOSFET begins conducting (via its
body diode or enhancement channel), the current in the
upper MOSFET decreases to zero. In Equation 27, the
required time for this commutation is t₁and the associated
power loss is P_UMOS,1.
P_{U M O S ,1}
≈
V_IN
⎛
⎜
-^I-^O-----^U----^T--
⎝^N
+
I_{--L----,-P----P--⎟⎞}
2_⎠
⎛
⎜
⎝
-^t-¹--
⎞
⎟
2_⎠
f_S
(EQ. 27)
Similarly, the upper MOSFET begins conducting as soon as
it begins turning on. Assuming the inductor current is in the
positive domain, the upper MOSFET sees approximately the
input voltage applied across its drain and source terminals,
while it turns on and starts conducting the inductor current.
This transition occurs over a time t₂, and the approximate
the power loss is P_UMOS,2.
P_UMOS,
2
≈
V_IN
⎛
⎜
⎝
-^I-^O-----^U----^T--
N
–
-^I-^L----^,-^P----^P--⎟⎞
2_⎠
⎛
⎜
⎝
-^t-²--
⎞
⎟
2_⎠
f_S
(EQ. 28)
A third component involves the lower MOSFET’s reverse-
recovery charge, Q_RR. Since the lower MOSFET’s body
diode conducts the full inductor current before it has fully
switched to the upper MOSFET, the upper MOSFET has to
provide the charge required to turn off the lower MOSFET’s
body diode. This charge is conducted through the upper
MOSFET across VIN, the power dissipated as a result,
P_UMOS,3 can be approximated as:
P_UMOS,3 = V_IN Q_rr f_S
(EQ. 29)
23
FN9243.3
May 28, 2009