ISL6567 Datasheet, PDF (19/26 Pages) Intersil Corporation – Multipurpose Two-Phase Buck PWM Controller with Integrated MOSFET Drivers

ISL6567
operation at the lowest input voltage and choose a power
rating corresponding to the highest bias current that the
ISL6567 may require to drive the switching MOSFETs.
ISL6567
EXTERNAL CIRCUIT
PVCC
POR
CIRCUIT
V_IN
Q1
VCC
R1
(optional)
E/A _-
+
VREF
VREG
R2
SHUNT REGULATOR
FIGURE 22. INTERNAL SHUNT REGULATOR USE WITH
EXTERNAL NPN TRANSISTOR (ACTIVE
CONFIGURATION)
FREQUENCY COMPENSATION
The ISL6567 multi-phase converter behaves in a similar
manner to a voltage-mode controller. This section highlights
the design consideration for a voltage-mode controller requiring
external compensation. To address a broad range of
applications, a type-3 feedback network is recommended
(see Figure 23).
C2
R2 ^C1
COMP
FB
C3
R1
R3
ISL6567
V_DIFF (V_OUT)
FIGURE 23. COMPENSATION CONFIGURATION FOR ISL6567
CIRCUIT
Figure 24 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, applicable, with a small
number of adjustments, to the multi-phase ISL6567 circuit. The
output voltage (V_OUT) is regulated to the reference voltage,
VREF, level. The error amplifier output (COMP pin voltage) is
compared with the oscillator (OSC) modified saw-tooth wave to
provide a pulse-width modulated wave with an amplitude of V_IN
at the PHASE node. The PWM wave is smoothed by the output
filter (L and C). The output filter capacitor bank’s equivalent
series resistance is represented by the series resistor E.
C2
COMP
R2 _C1
-
FB
E/A ⁺
VREF
R3 ^C3
R1
Ro
VDIFF
-
RGND
+
VSEN
PWM
CIRCUIT
OSCILLATOR
V_OSC
HALF-BRIDGE
DRIVE
V_IN
L
UGATE
PHASE
LGATE
V_OUT
D
C
E
ISL6567 EXTERNAL CIRCUIT
FIGURE 24. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer
function of V_OUT/V_COMP. This function is dominated by a DC
gain, given by d_MAXV_IN/V_OSC, and shaped by the output
filter, with a double pole break frequency at F_LC and a zero at
F_CE. For the purpose of this analysis, L and D represent the
individual channel inductance and its DCR divided by 2
(equivalent parallel value of the two output inductors), while C
and E represents the total output capacitance and its
equivalent series resistance.
F_LC=
-------------¹--------------
2π ⋅ L ⋅ C
F_CE=
-----------¹------------
2π ⋅ C ⋅ E
(EQ. 14)
The compensation network consists of the error amplifier
(internal to the ISL6567) and the external R₁ to R₃, C₁ to C₃
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F₀; typically 0.1 to 0.3 of F_SW) and adequate phase
margin (better than 45 °). Phase margin is the difference
between the closed loop phase at F_0dB and 180°. The
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R₁, R₂, R₃, C₁, C₂, and
19
FN9243.3
May 28, 2009