ISL6567 Datasheet, PDF (22/26 Pages) Intersil Corporation – Multipurpose Two-Phase Buck PWM Controller with Integrated MOSFET Drivers

ISL6567
The power components should be placed first. Locate the
input capacitors close to the power switches. Minimize the
length of the connections between the input capacitors, C_IN,
and the power switches. Locate the output inductors and
output capacitors between the MOSFETs and the load.
Locate all the high-frequency decoupling capacitors
(ceramic) as close as practicable to their decoupling target,
making use of the shortest connection paths to any internal
planes, such as vias to GND immediately next, or even onto
the capacitor’s grounded solder pad.
The critical small components include the bypass capacitors
for VCC and PVCC. Locate the bypass capacitors, C_BP,
close to the device. It is especially important to locate the
components associated with the feedback circuit close to
their respective controller pins, since they belong to a
high-impedance circuit loop, sensitive to EMI pick-up. It is
important to place the R_ISEN resistors close to the
respective terminals of the ISL6567.
A multi-layer printed circuit board is recommended. Figure 26
shows the connections of the critical components for one output
channel of the converter. Note that capacitors C_xxIN and
C_xxOUT could each represent numerous physical capacitors.
Dedicate one solid layer, usually the one underneath the
component side of the board, for a ground plane and make all
critical component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break this
plane into smaller islands of common voltage levels. Keep the
metal runs from the PHASE terminal to inductor L_OUT short.
The power plane should support the input power and output
power nodes. Use copper filled polygons on the top and bottom
circuit layers for the phase nodes. Use the remaining printed
circuit layers for small signal wiring.
+12V_IN
+5V_IN
R_EN
C₂
R₂
R₁
(C_F1)
REFTRK
FS
R_{FS SS}
C_SS
MON
R_PG
PGOOD
EN
(C_F2)
L_IN
C_BIN1
(C_HFIN1)
VCC
PVCC
ISL6567
BOOT1
UGATE1
C_BOOT1
Q1
PHASE1
ISEN1 _RISEN1
LGATE1
L_OUT1
Q2
BOOT2
C_BOOT2
UGATE2
C_BIN2
Q3
(C_HFIN2)
LOCATE NEAR LOAD
(MINIMIZE CONNECTION PATH)
C_BOUT
V_OUT
(C_HFOUT)
COMP
PHASE2
C₁
ISEN2 _RISEN2
L_OUT2
R_S
LGATE2
Q4
PGND
FB
VDIFF VSEN RGND
GND
R_P
LOCATE NEAR SWITCHING TRANSISTORS
(MINIMIZE CONNECTION PATH)
LOCATE CLOSE TO IC
(MINIMIZE CONNECTION PATH)
KEY
HEAVY TRACE ON CIRCUIT PLANE LAYER
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 26. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
22
FN9243.3
May 28, 2009