ISL6123_07 Datasheet, PDF (8/21 Pages) Intersil Corporation – Power Sequencing Controllers

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
TABLE 1.
NOMINAL DELAY TO SEQUENCING THRESHOLD
DLY PIN CAPACITANCE
TIME(s)
Open
0.00006
100pF
0.00013
1000pF
0.0013
0.01μF
0.013
0.1μF
0.13
1μF
1.3
10μF
13
NOTE: Nom. T_{DEL_SEQ} = Cap (μF) * 1.3MΩ.
l
Figure 2 illustrates the turn-on and Figure 3 illustrates the
nominal turnoff timing diagram of the ISL6123 and ISL6124
product.
The ISL6125 is similar to the ISL6124 except that instead of
charge pumped GATE outputs, there are sequenced open
drain outputs that can be pulled up to a maximum of V_DD.
Note the delay and flexible sequencing possibilities. Multiple
series, parallel or adjustable capacitors can be used to easily
fine tune timing between that offered by standard value
capacitors.
UVLO_A
UVLO_B
UVLO_C
UVLO_D
ENABLE# (ISL6124)
ENABLE (ISL6123)
DLYON_B
DLYON_D
DLYON_A
DLYON_C
GATE_B
GATE_D
GATE_C
GATE_A
V_UVLOVth
V_UVLOVth
V_UVLOVth
V_UVLOVth
T_UVLOdel
V_EN
<TFIL
DLY_Vth
DLY_Vth
DLY_Vth
DLY_Vth
V_QPUMP-1V
T_RSTdel
V_QPUMP
V_QPUMP
V_QPUMP
V_QPUMP
RESET#
FIGURE 2. ISL6123, ISL6124 TURN-ON AND GLITCH RESPONSE TIMING DIAGRAM
8
FN9005.8
February 5, 2007