ISL6123_07 Datasheet, PDF (7/21 Pages) Intersil Corporation – Power Sequencing Controllers

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
The ISL6123 and ISL6124 have the same functionality
except for the ENABLE active polarity with the ISL6124
having an ENABLE# input. Additionally the ISL6123 and
ISL6130 also have an ultra low power sleep state when
ENABLE is low.
The ISL6125 has the same personality as the ISL6124 but
instead of charged pump driven GATE outputs it has open
drain outputs that can be pulled up to a maximum of V_DD.
The ISL6126 and ISL6130 are different in that their
sequence on is not time determined but voltage
determined. Its personality is that each of the four channels
operates independently so that once the IC is biased and
any one of the UVLO inputs is greater than the 0.63V
internal reference, and the enable input is also satisfied the
GATE for the associated UVLO input will turn-on. In turn,
the other UVLO inputs need to be satisfied for the
associated GATEs to turn-on. 150ms after all GATEs are
fully on (GATE voltage = VQP), the RESET# is released to
go high. The UVLO inputs can be driven by either a
previously turned on output rail offering a voltage
determined sequence or by logic signal inputs. Any
subsequent UVLO level < its programmed level will pull the
associated GATE and RESET# output low (if previously
released), but will not latch-off the other GATEs.
Predetermined turn-off is accomplished by deasserting
enable, this will cause RESET# to latch low and all four
GATE outputs to follow the programmed turn off sequence
similar to a ISL6124.
The ISL6127 is a four-channel sequencer pre-programmed
for A-B-C-D turn-on and D-C-B-A turn-off. After all four
UVLO and ENABLE# inputs are satisfied for ~10ms, the
sequencing starts and the next GATE in the sequence
starts to ramp up once the previous GATE has reached
~VQP-1V. 160ms after the last GATE is at VQP the
RESET# output will be deasserted. Once any UVLO is
unsatisfied, RESET# is pulled low, SYSRST# is pulled low
and all GATEs are simultaneously turned off. When
ENABLE# is signaled high the D GATE will start to pull low
and once below 0.6V the next GATE will then start to pull
low and so on until all GATEs are at 0V. Unloaded, this turn
off sequence will complete in <1ms. This variant offers a
lower cost and size implementation as the external delay
caps are not used. Since the delay caps are not used this
IC can not delay the start of subsequent GATEs thus
necessary stabilization or system house keeping need to
be considered.
The ISL6128 is a four-channel device that groups the four
channels into two groups of two channels each, as A, B
and C, D, each group having its own ENABLE# and
RESET# I/IO pins. This requires all four UVLO and both
ENABLE#s to be satisfied for sequencing to start. The A, B
group will first turn on 10ms after the second ENABLE# is
pulled low with A then B turning on followed by C then D.
Once the preceding GATE = VQP the next DLY_ON pin
starts to charge its capacitor thus turning on all four GATEs.
Approximately 160ms after D GATE = VQP the RESET#
output is released to go high. Once any UVLO is unsatisfied,
only the related group’s RESET# and two GATEs are pulled
low. The related EN input has to be cycled for the faulted
group to be turned-on again. Normal shutdown is invoked by
either signaling both ENABLE# inputs high which will cause all
the two related GATEs to shutdown in reverse order from turn-
on. DLY_X caps adjust the delay between GATES during turn
on and off but not the order.
During bias up the RESET# output is guaranteed to be in the
correct state with V_DD lower than 1V.
The SYSRST# pin follows the V_DD upon power up with a
weak internal pull-up and is both an input and output
connection providing two functions. As an input, if it is pulled
low all GATEs will be unconditionally shut off and RESET#
pulls low, see Figure 6. This input can also be used as a no
wait enabling input, if all inputs (ENABLE and UVLO) are
satisfied it does not wait through the ~10ms enable delay to
initiate DLY_ON cap charging when released to go high. As
an output it is useful when implementing multiple sequencers
in a design needing simultaneous shutdown as with a kill
switch across all sequencers. Once any UVLO is unsatisfied
longer than T_FIL the related SYSRST# will pull low and pull all
other SYSRST# inputs low that are on a common connection
thus unconditionally shutting down all outputs across multiple
sequencers.
Except for ISL6128 after a fault, restart of the turn on
sequence is automatic once all requirements are met. This
allows for no interaction between the sequencer and a
controller IC if desired. The ENABLE & RESET# I/O do allow
for a higher level of feedback and control if desired. The
ISL6128 requires that the related ENABLE# be cycled for
restart of its associated group GATEs. If no capacitors are
connected between DLY_ON or DLY_OFF pins and ground
then all such related GATEs start to turn on immediately after
the 10ms (T_UVLOdel) ENABLE stabilization time out has
expired and the GATEs start to immediately turn off when
ENABLE is asserted.
If some of the rails are to be sequenced together, in order to
eliminate the effect of capacitor variance on the timing and to
reduce cost, a common capacitor can be connected to two or
more DLY_ON or DLY_OFF pins. In this case multiply the
capacitor value by the number of common DLY_X pins to
retain the desired timing.
Table 1 illustrates the nominal time delay from the start of
charging to the 1.27V reference for various capacitor values
on the DLY_X pins. This table does not include the 10ms of
enable lock out delay during a start up sequence but
represents the time from the end of the enable lock out delay
to the start of GATE transition. There is no enable lock out
delay for a sequence off, so this table illustrates the delay to
GATE transition from a disable signal.
7
FN9005.8
February 5, 2007