ISL6123_07 Datasheet, PDF (6/21 Pages) Intersil Corporation – Power Sequencing Controllers

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Electrical Specifications
PARAMETER
V_DD = 1.5V to +5V, T_A = T_J = -40°C to +85°C, unless otherwise specified. (Continued)
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
SYSRST# Pull-Up Voltage
Vpu_srst
V_DD
SYSRST# Pull-Down Current
Ipu_1.5
V_DD = 1.5V
5
Ipu_5
V_DD = 5V
100
SYSRST# Low Output Voltage
Vol_srst
V_DD = 1.5V, I_OUT = 100μA
150
SYSRST# Output Capacitance
Cout_srst
10
SYSRST# Low to GATE Turn-Off
T_{delSYS_G} GATE = 80% of V_DD+5V
40
GATE
GATE Turn-On Current
GATE Turn-Off Current
GATE Current Range
GATE Turn-On/Off Current Temp. Coeff.
GATE Pull-Down High Current
GATE High Voltage
GATE Low Voltage
BIAS
I_GATEon
I_{GATEoff_l}
I_{GATE_range}
TC_I_GATE
I_{GATEoff_h}
V_GATEh
V_GATEh
V_GATEl
GATE = 0V
GATE = V_DD, Disabled
Within IC I_GATE max-min
GATE = V_DD, UVLO = 0V
V_DD < 2V, T_J = +25°C
V_DD > 2V
Gate Low Voltage, V_DD = 1V
0.8
1.1
1.4
-1.4
-1.05
-0.8
0.35
0.2
88
V_DD+4.9V
V_DD+5V V_DD+5.3V
0
0.1
IC Supply Current
ISL6123, ISL6130 Stand By IC Supply
Current
I_{VDD_5V}
I_{VDD_3.3V}
I_{VDD_1.5V}
I_{VDD_sb}
V_DD = 5V
V_DD = 3.3V
V_DD = 1.5V
V_DD = 5V, ENABLE = 0V
0.20
0.5
0.14
0.10
1
V_DD Power On Reset
V_DD_POR
1
UNIT
V
μA
μA
mV
pF
ns
μA
μA
μA
nA/°C
mA
V
V
V
mA
mA
mA
μA
V
Descriptions and Operation
The ISL612X sequencer family consists of several four
channel voltage sequencing controllers in various
functional and personality configurations. All are designed
for use in multiple-voltage systems requiring power
sequencing of various supply voltages. Individual voltage
rails are gated on and off by external N-Channel MOSFETs,
the gates of which are driven by an internal charge pump to
V_DD +5.3V (VQP) in a user programmed sequence.
With the four-channel ISL6123 the ENABLE must be
asserted high and all four voltages to be sequenced must
be above their respective user programmed Under Voltage
Lock Out (UVLO) levels before programmed output turn on
sequencing can begin. Sequencing and delay
determination is accomplished by the choice of external
cap values on the DLY_ON and DLY_OFF pins. Once all
four UVLO inputs and ENABLE are satisfied for 10ms, the
four DLY_ON caps are simultaneously charged with 1µA
current sources to the DLY_Vth level of 1.27V. As each
DLY_ON pin reaches the DLY_Vth level its associated
GATE will then turn-on with a 1µA source current to the
VQP voltage of V_DD+5.3V. Thus all four GATEs will
sequentially turn on. Once at DLY_Vth the DLY_ON pins
will discharge to be ready when next needed. After the
entire turn on sequence has been completed and all
GATEs have reached the charge pumped voltage (VQP), a
160ms delay is started to ensure stability after which the
RESET# output will be released to go high. Subsequent to
turn-on, if any input falls below its UVLO point for longer
than the glitch filter period (~30μs) this is considered a
fault. RESET# and SYSRST# are pulled low and all GATEs
are simultaneously also pulled low. In this mode the GATEs
are pulled low with 88mA. Normal shutdown mode is
entered when no UVLO is violated and the ENABLE is
deasserted. When ENABLE is deasserted, RESET# is
asserted and pulled low. Next, all four shutdown ramp caps
on the DLY_OFF pins are charged with a 1μA source and
when any ramp-cap reaches DLY_Vth, a latch is set and a
current is sunk on the respective GATE pin to turn off its
external MOSFET. When the GATE voltage is
approximately 0.6V, the GATE is pulled down the rest of the
way at a higher current level. Each individual external FET
is thus turned off removing the voltages from the load in the
programmed sequence.
6
FN9005.8
February 5, 2007