ISL6123_07 Datasheet, PDF (11/21 Pages) Intersil Corporation – Power Sequencing Controllers

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Figures 9 and 10 illustrate the timing relationships between the
EN input, RESET#, DLY and GATE outputs and the VOUT
voltage for a single channel being turned on and off
respectively. RESET# is not shown in Figure 9 as it asserts
160ms after the last GATE goes high.
All IC family variants share similar function for DLY_X capacitor
charging, GATE and RESET# operation. Figures 11 through 14
illustrate the principal feature and functional differences for
each of the ISL6125, ISL6126, ISL6127 and ISL6128 variants.
Figure 11 features the ISL6125 open drain outputs being
sequenced on and off along with RESET# relationship which is
similar to all other family variants.
Figure 12 illustrates the independent input feature of the
ISL6126 which allows once the EN# is low for each UVLO to be
individually satisfied and for its associated GATE to turn-on.
Only when the last variable VIN is satisfied as shown does the
RESET# release to signal all input voltages are valid.
Typical Performance Waveforms
Figure 13 shows the ISL6127 pre-programmed ABCD on
DCBA off order of sequencing with minimal non-adjustable
delay between each.
Figure 14 demonstrates the independence of the redundant
two rail sequencer. It shows that either one of the two groups
can be turned off and the ABCD order of restart with
capacitor programmable delay once both EN inputs are
pulled low.
Using the ISL6125EVAL1 Platform
The ISL6125EVAL1 is the ISL6125 specific evaluation board
providing for easy evaluation of the ISL6125 with its unique
open drain outputs. The UVLO levels, sequence and delays
are programmed exactly like the other ISL612X ICs but the
ISL6125 has sequenced open drain outputs rather than
charge pumped driven GATE outputs. See Figure 16 for its
schematic and photograph.
5VOUT
ENABLE#
3.3VOUT
2.5VOUT
1.5VOUT
RESET#
1V/DIV
40ms/DIV
FIGURE 7. ISL6124 SEQUENCED TURN-ON
T_delENLO
GATE 2V/DIV
3.3VO 1V/DIV
DLY_Vth
DLY_ON 1V/DIV
EN 2V/DIV
10ms/DIV
FIGURE 9. ISL6123 SINGLE CHANNEL TURN-ON
5VOUT
3.3VOUTPUT
1.5VOUT
2.5VOUT
ENABLE#
1V/DIV
20ms/DIV
FIGURE 8. ISL6124 SEQUENCED TURN-OFF
GATE 2V/DIV
3.3VO 1V/DIV
RESET# 2V/DIV
EN 2V/DIV
DLY_OFF 1V/DIV
DLY_Vth
4ms/DIV
FIGURE 10. ISL6123 SINGLE CHANNEL TURN-OFF
11
FN9005.8
February 5, 2007