ISL6123_07 Datasheet, PDF (19/21 Pages) Intersil Corporation – Power Sequencing Controllers

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Negative Voltage Sequencing
The ISL612X family can use the charged pump GATE output
to drive FETs that would control and sequence negative
voltages down to a nominal -5V with minimal additional
external circuitry. Figure 22 shows turn-on of 5V bipolar
supplies together, then the +2.5V and turn-off of both
positive supplies being turned off together after the -5V.
Figure 23 shows the minimal additional external circuitry to
accomplish this. The 5V zener diode is used to level shift the
GATE drive down 5V to prevent premature turn-on when
GATE = 0V. Once GATE drive voltage > Vz, then FET
Vgs > 5V, ensuring full turn-on once GATE gets to
VDD+5.3V. Turn-on and turn-off ramp rate can be adjusted
with FET gate series resistor value. Sequencing of the -V rail
is accomplished as normal via the DLY_X capacitor value
although adjustments in prototyping should be factored in to
fine tune for actual circuit requirements.
Figures 24 and 25 illustrate a high accuracy -V detection
circuit using the ISL6131 and a low cost low accuracy -V
detect circuit and respectively.
+V
R1
+BIAS
R3
(1k)
ISL6131
VMON
OR
R2
ISL6536A _PGOOD R4
(15K)
-BIAS
-V
R5
(10k)
Q1 Si1300DL
OR EQUIV.
TO UVLO OF
ISL612X FOR
R6 ^{-V CONTROL AND}
SEQUENCING
R1 and R2 define -V UVLO level
R3 ensures supervisor (ISL6131 or ISL6536A) PGOOD pull-up
R4 and R5 provide Q1 gate bias between 0V and +V
to 0V (resistor values suitable for -V = -5V and +V = +3.3V)
FIGURE 24. HGH ACCURACY -V LOCK OUT
+V
R1
R2
-V
TO UVLO OF ISL612X FOR CONTROL
AND SEQUENCING OF -V
Chose R1 and R2 values to drive UVLO
high when -V is sufficiently present
FIGURE 25. LOW ACCURACY -V PRESENCE DETECTION
FIGURE 22. ±VOLTAGE SEQUENCING
-Vin
-Vout
Application Considerations
Timing Error Sources
In any system there are variance contributors, for the ISL612X
family the timing errors are mainly contributed by three sources.
Capacitor Timing Mismatch Error
Obviously, the absolute capacitor value is an error source,
thus lower percentage tolerance capacitors help to reduce
this error source. Figure 26 illustrates a difference of 0.57ms
between two DLY_X outputs ramping to DLY_X threshold
voltage, these 5% capacitors were from a common source.
In applications where two or more GATEs or LOGIC outputs
must have concurrent transitions, it is recommended that a
common GATE drive be used to eliminate this timing error.
R1
ISL612X GATE
Additional 2 components
D1
necessary for -V control
and sequencing.
D1 necessary to prevent premature turn-on. R1 is used to hold
FET Vgs = 0V until D1 Vz is overcome. R1 value can be changed to
adjust -V ramp rates. Choose a R1 value between 4MΩ and 10MΩ
initially and fine tune resistor value for the particular need.
FIGURE 23. -VOLTAGE FET DRIVE CIRCUIT
FIGURE 26. CAPACITOR TIMING MISMATCH
19
FN9005.8
February 5, 2007