ISL6123_07 Datasheet, PDF (5/21 Pages) Intersil Corporation – Power Sequencing Controllers

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Absolute Maximum Ratings
V_DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V_DD+6V
ISL6125 LOGIC OUT. . . . . . . . . . . . . . . . . . . . . -0.3V to V_DD +0.3V
UVLO, ENABLE, ENABLE#, SYSRST# . . . . . . -0.3V to V_DD +0.3V
RESET#, DLY_ON, DLYOFF . . . . . . . . . . . . . . . -0.3V to V_DD +0.3V
Operating Conditions
V_DD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . +1.5V to +5.5V
Temperature Range (T_A) . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) θ_JA (°C/W) θ_JC (°C/W)
4 x 4 QFN Package . . . . . . . . . . . . . . .
48
9
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . +125°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(QFN - Leads Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ_JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. For θ_JC, the “case temp” location is the center of the exposed metal pad on the package underside.
3. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications V_DD = 1.5V to +5V, T_A = T_J = -40°C to +85°C, unless otherwise specified.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
UVLO
Falling Undervoltage Lockout Threshold
V_UVLOvth T_J = +25°C
619
633
Undervoltage Lockout Threshold Tempco
TC_UVLOvth T_J = -40°C to +85°C
40
Undervoltage Lockout Hysteresis
V_UVLOhys
10
Undervoltage Lockout Threshold Range
RUVLOvth Max V_UVLOvth- Min V_UVLOvth
7
Undervoltage Lockout Delay
TUVLOdel ENABLE satisfied
10
Transient Filter Duration
DELAY ON/OFF
TFIL
V_DD, UVLO, ENABLE glitch filter
30
Delay Charging Current
Delay Charging Current Range
DLY_ichg V_DLY = 0V
0.92
1
DLY_ichg_r DLY_ichg(max) - DLY_ichg(min)
0.08
Delay Charging Current Temp. Coeff.
TC_DLY_ichg
0.2
Delay Threshold Voltage
DLY_Vth
1.238
1.266
Delay Threshold Voltage Temp. Coeff.
TC_DLY_Vth
0.2
ENABLE/ENABLE#, RESET# & SYSRST# I/O
ENABLE Threshold
ENABLE# Threshold
ENABLE/ENABLE# Hysteresis
ENABLE/ENABLE# Lockout Delay
V_ENh
V_ENh
V_{ENh -}V_ENl
TdelEN_LO
Measured at V_DD = 1.5V
UVLO satisfied
1.2
0.5 V_DD
0.2
10
ENABLE/ENABLE# Input Capacitance
Cin_en
5
RESET# Pull-up Voltage
RESET# Pull-Down Current
RESET# Delay after GATE High
RESET# Output Low
Vpu_rst
I_RSTpd1
I_RSTpd3
I_RSTpd5
T_RSTdel
V_RSTl
V_DD = 1.5V, RST = 0.1V
V_DD = 3.3V, RST = 0.1V
V_DD = 5V, RST = 0.1V
GATE = V_DD+5V
Measured at V_DD = 5V with 5k
pull-up resistors
V_DD
5
13
17
160
RESET Output Capacitance
Cout_rst
10
MAX
UNIT
647
mV
nV/°C
mV
mV
ms
μs
1.08
1.294
μA
μA
nA/°C
V
mV/°C
V
V
V
ms
pF
V
mA
mA
mA
ms
0.1
V
pF
5
FN9005.8
February 5, 2007