ISL12030 Datasheet, PDF (8/17 Pages) Intersil Corporation – Low Power RTC with 50/60 Cycle AC Input, Alarms and Daylight Savings Correction

ISL12030
TABLE 1. REGISTER MEMORY MAP (X indicates writes to these bits have no effect on the device) (Continued)
REG
BIT
ADDR SECTION NAME
7
6
5
4
3
2
1
0
RANGE DEFAULT
23h
SCA1
ESCA1 SCA122 SCA121 SCA120 SCA113 SCA112 SCA111 SCA110 0 to 59
00h
24h
MNA1 EMNA1 MNA122 MNA121 MNA120 MNA113 MNA112 MNA111 MNA110 0 to 59
00h
25h
HRA1 EHRA1
0
HRA121 HRA120 HRA113 HRA112 HRA111 HRA110 0 to 23
00h
Alarm1
26h
DTA1
EDTA1
0
DTA121 DTA120 DTA113 DTA112 DTA111 DTA110 1 to 31
01h
27h
MOA1 EMOA1
0
0
MOA120 MOA113 MOA112 MOA111 MOA110 1 to12
01h
28h
DWA1 EDWA1
0
0
0
0
DWA12 DWA11 DWA10
0 to 6
00h
8
FN6617.1
January 15, 2008