ISL12030 Datasheet, PDF (4/17 Pages) Intersil Corporation – Low Power RTC with 50/60 Cycle AC Input, Alarms and Daylight Savings Correction

ISL12030
I²C Interface Specifications Specifications apply for: V_DD = 2.7 to 5.5V, T_A = -40°C to +85°C,
unless otherwise stated. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 3) (Note 8) UNITS NOTES
C_PIN
f_SCL
t_IN
SDA and SCL Pin Capacitance
SCL Frequency
T_A = +25°C, f = 1MHz,
V_DD = 5V, V_IN = 0V,
V_OUT = 0V
Pulse Width Suppression Time at Any pulse narrower than the
SDA and SCL Inputs
max spec is suppressed.
10
pF
400
kHz
50
ns
t_AA
SCL Falling Edge to SDA Output SCL falling edge crossing
Data Valid
30% of V_DD, until SDA exits
the 30% to 70% of V_DD
window.
900
ns
t_BUF
Time the Bus Must be Free Before SDA crossing 70% of V_DD
1300
ns
the Start of a New Transmission during a STOP condition, to
SDA crossing 70% of V_DD
during the following START
condition.
t_LOW
Clock LOW Time
Measured at the 30% of V_DD
1300
ns
crossing.
t_HIGH
Clock HIGH Time
Measured at the 70% of V_DD
600
ns
crossing.
t_SU:STA
t_HD:STA
t_SU:DAT
t_HD:DAT
t_SU:STO
t_HD:STO
t_DH
t_R
t_F
Cb
START Condition Setup Time
SCL rising edge to SDA
600
falling edge. Both crossing
70% of V_DD.
START Condition Hold Time
From SDA falling edge
600
crossing 30% of V_DD to SCL
falling edge crossing 70% of
V_DD.
Input Data Setup Time
From SDA exiting the 30% to
100
70% of V_DD window, to SCL
rising edge crossing 30% of
V_DD.
Input Data Hold Time
From SCL falling edge
0
crossing 30% of V_DD to SDA
entering the 30% to 70% of
V_DD window.
STOP Condition Setup Time
From SCL rising edge
600
crossing 70% of V_DD, to SDA
rising edge crossing 30% of
V_DD.
STOP Condition Hold Time
From SDA rising edge to
600
SCL falling edge. Both
crossing 70% of V_DD.
Output Data Hold Time
From SCL falling edge
0
crossing 30% of V_DD, until
SDA enters the 30% to 70%
of V_DD window.
SDA and SCL Rise Time
From 30% to 70% of V_DD. 20 + 0.1 x Cb
SDA and SCL Fall Time
From 70% to 30% of V_DD. 20 + 0.1 x Cb
Capacitive loading of SDA or SCL Total on-chip and off-chip
10
ns
ns
ns
900
ns
ns
ns
ns
300
ns
7
300
ns
7
400
pF
7
4
FN6617.1
January 15, 2008