ISL12030 Datasheet, PDF (11/17 Pages) Intersil Corporation – Low Power RTC with 50/60 Cycle AC Input, Alarms and Daylight Savings Correction

ISL12030
ADDRESS FUNCTION
7
15h Month Forward DSTE
16h
Day Forward
0
17h Date Forward
0
18h Hour Forward HrFdMIL
TABLE 5. DST FORWARD REGISTERS
6
5
4
3
0
0
MoFd20
MoFd13
DwFdE
WkFd12
WkFd11
WkFd10
0
DtFd21
DtFd20
DtFd13
0
HrFd21
HrFd20
HrFd13
2
MoFd12
DwFd12
DtFd12
HrFd12
1
MoFd11
DwFd11
DtFd11
HrFd11
0
MoFd10
DwFd10
DtFd10
HrFd10
ADDRESS
NAME
19h Month Reverse
1Ah
Day Reverse
1Bh Date Reverse
1Ch Hour Reverse
7
0
0
0
HrRvMIL
TABLE 6. DST REVERSE REGISTERS
6
5
4
3
0
0
MoRv20
MoRv13
DwRvE
WkRv12
WkRv11
WkRv10
0
DtRv21
DtRv20
DtRv13
0
HrRv21
HrRv20
HrRv13
2
MoRv12
DwRv12
DtRv12
HrRv12
1
MoRv11
DwRv11
DtRv11
HrRv11
0
MoRv10
DwRv10
DtRv10
HrRv10
ALARM Registers (1Dh to 28h)
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
enabled for a match.
There are two alarm operation modes: Single Event and
periodic Interrupt Mode.
Single Event Mode is enabled by setting either ALE0 or
ALE1 to 1, then setting bit 7 on any of the Alarm registers
(ESCA... EDWA) to “1”, and setting the IM bit to “0”. This
mode permits a one-time match between the Alarm registers
and the RTC registers. Once this match occurs, the ALM bit
is set to “1” and the IRQ output will be pulled LOW and will
remain LOW until the ALM bit is reset. This can be done
manually or by using the auto-reset feature. Since the IRQ
output is shared by both alarms, they both need to be reset
in order for the IRQ output to go HIGH.
Interrupt Mode is enabled by setting either ALE0 or ALE1 to
1, then setting bit 7 on any of the Alarm registers (ESCA...
EDWA) to “1”, and setting the IM bit to “1”. Setting the IM bit
to 1 puts both ALM0 and ALM1 into Interrupt mode. The IRQ
output will now be pulsed each time an alarm occurs (either
AL0 or AL1). This means that once the interrupt mode alarm
is set, it will continue to alarm until it is reset.
To clear a single event alarm, the corresponding ALM0 or
ALM1 bit in the SRDC register must be set to “0” with a write.
Note that if the ARST bit is set to “1” (address 0Ch, bit 7), the
ALM0 and ALM1 bits will automatically be cleared when the
status register is read.
The IRQ output will be set by an alarm match for either
ALM0 or ALM1.
Following are examples of both Single Event and periodic
Interrupt Mode alarms.
Example 1
• Alarm set with single interrupt (IM = ”0”)
• A single alarm will occur on January 1 at 11:30am.
• Set Alarm registers as follows:
BIT
ALARM
REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION
SCA0 0 0 0 0 0 0 0 0 00h Seconds disabled
MNA0 1 0 1 1 0 0 0 0 B0h Minutes set to 30,
enabled
HRA0 1 0 0 1 0 0 0 1 91h Hours set to 11,
enabled
DTA0
1 0 0 0 0 0 0 1 81h Date set to 1,
enabled
MOA0 1 0 0 0 0 0 0 1 81h Month set to 1,
enabled
DWA0 0 0 0 0 0 0 0 0 00h Day of week
disabled
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30 a.m. on January 1 (after
seconds changes from 59 to 00) by setting the ALM0 bit in the
status register to “1” and also bringing the IRQ output LOW.
11
FN6617.1
January 15, 2008