ISL12030 Datasheet, PDF (6/17 Pages) Intersil Corporation – Low Power RTC with 50/60 Cycle AC Input, Alarms and Daylight Savings Correction

ISL12030
General Description
The ISL12030 device is a low power real time clock with
50/60 AC input for timing synchronization, clock/calendar
registers, single periodic or polled alarms. There are 128
bytes of user SRAM.
The oscillator uses a 50/60 cycle sine wave input. The real
time clock tracks time with separate registers for hours,
minutes and seconds. The calendar registers contain the
date, month, year and day of the week. The calendar is
accurate through year 2100, with automatic leap year
correction and auto daylight savings correction.
The ISL12030’s alarm can be set to any clock/calendar
value for a match. Each alarm’s status is available by
checking the Status Register. The device also can be
configured to provide a hardware interrupt via the IRQ pin.
There is a repeat mode for the alarms allowing a periodic
interrupt every minute, every hour, every day, etc.
The ISL12030 devices are specified for V_DD = 2.7V to 5.5V
Pin Descriptions
AC (AC Input)
The AC input is the main clock input for the real time clock. It
can be either 50Hz or 60Hz, sine wave. The preferred
amplitude is 2.5V_P-P, although amplitudes >0.2 x V_DD are
acceptable. An AC coupled (series capacitor) sine wave
clock waveform is desired as the AC clock input provides DC
biasing.
IRQ (Interrupt Output)
This pin provides an interrupt signal output. This signal
notifies a host processor that an alarm has occurred and
requests action. It is an open drain active LOW output.
Serial Clock (SCL)
The SCL input is used to clock all serial data into and out of
the device. The input buffer on this pin is always active (not
gated). It is disabled when the V_DD supply drops below 2.7V.
Serial Data (SDA)
SDA is a bi-directional pin used to transfer data into and out
of the device. It has an open drain output and may be OR’ed
with other open drain or open collector outputs. The input
buffer is always active (not gated) in normal mode.
An open drain output requires the use of a pull-up resistor.
The output circuitry controls the fall time of the output signal
with the use of a slope controlled pull-down. The circuit is
designed for 400kHz I²C interface speeds.
V_DD, GND
Chip power supply and ground pins. The device will operate
with a power supply from V_DD = 2.7V to 5.5VDC. A 0.1µF
capacitor is recommended on the V_DD pin to ground.
Functional Description
Power Supply Operation
The ISL12030 will function with inputs from V_DD = 2.7V to
5.5VDC. If the V_DD supply should drop below this, operation
to the specifications may be compromised, although the
SRAM memory will hold its values until V_DD = 1.8V. Below
that, the entire device is not guaranteed to operate or retain
SRAM memory.
Power Failure Detection
The ISL12030 provides a Real Time Clock Failure Bit
(RTCF) to detect total power failure. It allows users to
determine if the device has powered up after having lost all
power to the device (V_DD very near 0.0VDC).
Real Time Clock Operation
The Real Time Clock (RTC) maintains an accurate internal
representation of tenths of a second, second, minute, hour,
day of week, date, month and year. The RTC also has
leap-year correction. The clock also corrects for months
having fewer than 31 days and has a bit that controls 24
hour or AM/PM format. When the ISL12030 powers up after
the loss of V_DD, the clock will not begin incrementing until at
least one byte is written to the clock register.
Alarm Operation
The alarm mode is enabled via the MSB bit. Single event or
interrupt alarm mode is selected via the IM bit. The standard
alarm allows for alarms of time, date, day of the week,
month and year. When a time alarm occurs in single event
mode, the IRQ pin will be pulled low and the corresponding
alarm status bit (ALM0 or ALM1) will be set to “1”. The
status bits can be written with a “0” to clear, or if the ARST
bit is set, a single read of the SRDC status register will
clear them.
The pulsed interrupt mode (setting the IM bit to “1”) activates
a repetitive or recurring alarm. Hence, once the alarm is set,
the device will continue to output a pulse for each occurring
match of the alarm and present time. The Alarm pulse will
occur as often as every minute (if only the nth second is set)
or as infrequently as once a year (if at least the nth month is
set). During pulsed interrupt mode, the IRQ pin will be pulled
LOW for 250ms and the alarm status bit (ALM0 or ALM1) will
be set to “1”.
General Purpose User SRAM
The ISL12030 provides 128 bytes of user SRAM. The SRAM
is volatile and will be lost or corrupted if V_DD drops below
1.8V.
I²C Serial Interface
The ISL12030 has an I²C serial bus interface that provides
access to the control and status registers and the user
SRAM. The I²C serial interface is compatible with other
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FN6617.1
January 15, 2008