ISL12030 Datasheet, PDF (7/17 Pages) Intersil Corporation – Low Power RTC with 50/60 Cycle AC Input, Alarms and Daylight Savings Correction

ISL12030
industry I²C serial bus protocols using a bi-directional data
signal (SDA) and a clock signal (SCL).
Register Descriptions
The registers are accessible following an I²C slave byte of
“1101 111x” and reads or writes to addresses [00h:47h]. The
defined addresses and default values are described in the
Table 1. The general purpose SRAM has a different slave
address (1010 111x), so it is not possible to read/write that
section of memory while accessing the registers.
REGISTER ACCESS
The contents of the registers can be modified by performing
a byte or a page write operation directly to any register
address.
The registers are divided into 5 sections. They are:
1. Real Time Clock (8 bytes): Address 00h to 07h.
2. Status (1 bytes): Address 08h.
3. Control (2 bytes): 0Ch and 13h.
4. Day Light Saving Time (8 bytes): 15h to 1Ch
5. Alarm 0/1 (12 bytes):1Dh to 28h
Write capability is allowable into the RTC registers (00h to
07h) only when the WRTC bit (bit 6 of address 0Ch) is set to
“1”. A multi-byte read or write operation is limited to one
section per operation. Access to another section requires a
new operation. A read or write can begin at any address
within the section.
A register can be read by performing a random read at any
address at any time. This returns the contents of that
register’s location. Additional registers are read by
performing a sequential read. For the RTC and Alarm
registers, the read instruction latches all clock registers into
a buffer, so an update of the clock does not change the time
being read. At the end of a read, the master supplies a stop
condition to end the operation and free the bus. After a read,
the address remains at the previous address +1 so the user
can execute a current address read and continue reading
the next register.
It is only necessary to set the WRTC bit prior to writing into
the RTC registers. All other registers are completely
accessible without setting the WRTC bit.
TABLE 1. REGISTER MEMORY MAP (X indicates writes to these bits have no effect on the device)
REG
BIT
ADDR SECTION NAME
7
6
5
4
3
2
1
0
RANGE DEFAULT
00h
SC
0
SC22
SC21
SC20
SC13
SC12
SC11
SC10
0 to 59
00h
01h
MN
0
MN22
MN21
MN20
MN13
MN12
MN11
MN10
0 to 59
00h
02h
HR
MIL
0
HR21
HR20
HR13
HR12
HR11
HR10
0 to 23
00h
03h
DT
0
RTC
04h
MO
0
0
DT21
DT20
DT13
DT12
DT11
DT10
1 to 31
01h
0
0
MO20
MO13
MO12
MO11
MO10
1 to 12
01h
05h
YR
YR23
YR22
YR21
YR20
YR13
YR12
YR11
YR10
0 to 99
00h
06h
DW
0
0
0
0
0
DW2
DW1
DW0
0 to 6
00h
07h
SS
0
0
0
0
SS3
SS2
SS1
SS0
0 to 9
00h
08h Status SRDC
0
DSTADJ ALM1
ALM0
0
0
0
RTCF
N/A
01h
0Ch
INT
ARST
WRTC
IM
X
X
X
ALE1
ALE0
N/A
01h
Control
13h
AC
AC5060 ACENB
X
X
X
X
X
X
N/A
00h
15h
DstMoFd DSTE
0
0
MoFd20 MoFd13 MoFd12 MoFd11 MoFd10 1 to 12
04h
16h
DstDwFd
0
DwFdE WkFd12 WkFd11 WkFd10 DwFd12 DwFd11 DwFd10
0 to 6
00h
17h
DstDtFd
0
0
DtFd21 DtFd20 DtFd13 DtFd12 DtFd11 DtFd10 1 to 31
01h
18h
DstHrFd HrFdMIL
0
HrFd21 HrFd20 HrFd13 HrFd12 HrFd11 HrFd10 0 to 23
02h
DSTCR
19h
DstMoRv
0
0
0
MoRv20 MoRv13 MoRv12 MoRv11 MoRv10 1 to 12
10h
1Ah
DstDwRv
0
DwRvE WkRv12 WkRv11 WkRv10 DwRv12 DwRv11 DwRv10 0 to 6
00h
1Bh
DstDtRv
0
0
DtRv21 DtRv20 DtRv13 DtRv12 DtRv11 DtRv10 1 to 31
01h
1Ch
DstHrRv HrRvMIL
0
HrRv21 HrRv20 HrRv13 HrRv12 HrRv11 HrRv10 0 to 23
02h
1Dh
SCA0
ESCA0 SCA022 SCA021 SCA020 SCA013 SCA012 SCA011 SCA010 0 to 59
00h
1Eh
MNA0 EMNA0 MNA021 MNA020 MNA013 MNA012 MNA011 MNA011 MNA010 0 to 59
00h
1Fh
HRA0 EHRA0
0
HRA021 HRA020 HRA013 HRA012 HRA011 HRA010 0 to 23
00h
Alarm0
20h
DTA0
EDTA0
0
DTA021 DTA020 DTA013 DTA012 DTA011 DTA010 1 to 31
01h
21h
MOA0 EMOA0
0
0
MOA020 MOA013 MOA012 MOA011 MOA010 1 to 12
01h
22h
DWA0 EDWA0
0
0
0
0
DWA02 DWA01 DWA00
0 to 6
00h
7
FN6617.1
January 15, 2008