ISL12030 Datasheet, PDF (13/17 Pages) Intersil Corporation – Low Power RTC with 50/60 Cycle AC Input, Alarms and Daylight Savings Correction

ISL12030
SCL
SDA
START
DATA
DATA
DATA
STABLE CHANGE STABLE
STOP
FIGURE 3. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
HIGH IMPEDANCE
START
ACK
FIGURE 4. ACKNOWLEDGE RESPONSE FROM RECEIVER
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
SIGNALS FROM
THE ISL12030
WRITE
S
T
A ^{IDENTIFICATION}
R
BYTE
T
ADDRESS
BYTE
11011110 0000
A
A
C
C
K
K
DATA
BYTE
S
T
O
P
A
C
K
FIGURE 5. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)
Device Addressing
Following a start condition, the master must output a Slave
Address Byte. The 7 MSBs are the device identifier. These bits
are “1101111b” for the RTC registers and “1010111b” for the
User SRAM.
The last bit of the Slave Address Byte defines a read or write
operation to be performed. When this R/W bit is a “1”, then a
read operation is selected. A “0” selects a write operation (see
Figure 6).
After loading the entire Slave Address Byte from the SDA bus,
the ISL12030 compares the device identifier and device select
bits with “1101111b” or “1010111b”. Upon a correct compare,
the device outputs an acknowledge on the SDA line.
Following the Slave Byte is a one byte word address. The word
address is either supplied by the master device or obtained
from an internal counter. On power-up the internal address
counter is set to address 00h, so a current address read starts
at address 00h. When required, as part of a random read, the
master must supply the 1 Word Address Byte as shown in
Figure 6.
In a random read operation, the slave byte in the “dummy write”
portion must match the slave byte in the “read” section. For a
random read of the Control/Status Registers, the slave byte
must be “1101111x” in both places.
13
FN6617.1
January 15, 2008