ISL12030 Datasheet, PDF (14/17 Pages) Intersil Corporation – Low Power RTC with 50/60 Cycle AC Input, Alarms and Daylight Savings Correction

ISL12030
.
1
1
0
1
11
1
R/W
SLAVE
ADDRESS BYTE
A7 A6 A5 A4 A3 A2 A1 A0 WORD ADDRESS
D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE
FIGURE 6. SLAVE ADDRESS, WORD ADDRESS AND DATA
BYTES
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL12030 responds with an ACK. At this time, the I²C
interface enters a standby state.
A multiple byte operation within a page is permitted. The
Address Byte must have the start address, and the data
bytes are sent in sequence after the address byte, with the
ISL12030 sending an ACK after each byte. The page write is
terminated with a STOP condition from the master. The
pages within the ISL12030 do not support wrapping around
for page read or write operations.
Read Operation
A Read operation consists of a three byte instruction
followed by one or more Data Bytes (see Figure 7). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the RW bit
set to “0”, an Address Byte, a second START, and a second
Identification byte with the RW bit set to “1”. After each of the
three bytes, the ISL12030 responds with an ACK. Then the
ISL12030 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eighth bit of each byte. The master terminates the read
operation (issuing a STOP condition) following the last bit of
the last Data Byte (see Figure 7).
The Data Bytes are from the memory location indicated by
an internal pointer. This pointers initial value is determined
by the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the last memory location in a section or page,
the master should issue a STOP. Bytes that are read at
addresses higher than the last address in a section may be
erroneous.
SIGNALS
FROM THE
MASTER
S
T _{IDENTIFICATION}
A
BYTE WITH
R
R/W=0
T
ADDRESS
BYTE
S
T _{IDENTIFICATION}
A _{BYTE WITH}
R
R/W = 1
T
S
A
A
T
C
C
O
K
K
P
SIGNAL AT
SDA
11011110
A
SIGNALS FROM
C
THE SLAVE
K
11011111
A
A
C
C _{FIRST READ}
K
K _{DATA BYTE}
LAST READ
DATA BYTE
FIGURE 7. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)
14
FN6617.1
January 15, 2008