ICL8052 Datasheet, PDF (8/21 Pages) Intersil Corporation – 14-Bit/16-Bit, Microprocessor- Compatible, 2-Chip, A/D Converter

ICL8052/ICL7104, ICL8068/ICL7104
System Electrical Specifications: ICL8068/ICL7104 V++ = +15V, V+ = +5V, V- = -15V, f_CLOCK = 200kHz (Note 16)
PARAMETER
TEST
CONDITIONS
ICL8068A/ICL7104-14
MIN
TYP MAX
ICL8068A/ICL7104-16
MIN
TYP MAX
UNITS
Zero Input Reading
Ratiometric Error (Note 13)
Linearity Over ± Full Scale (Error of
Reading from Best Straight Line)
V_IN = 0V, V_REF = 2V
V_IN = V_REF = 2V
-4V ≤ V_IN ≤ +4V
-00000
-1
-
±00000 +00000
0
1
0.5
1
-00000
-1
-
±00000 +00000
0
1
0.5
1
Counts
LSB
LSB
Differential Linearity (Difference
-4V ≤ V_IN ≤ +4V
between Worst Case Step of Adjacent
Counts and Ideal Step)
-
0.01
-
-
0.01
-
LSB
Rollover Error (Difference in Reading
for Equal Positive & Negative Voltage
Near Full Scale)
-V_IN = +V_IN ≅ 4V
-
0.5
1
-
0.5
1
LSB
Noise (P-P Value Not Exceeded 95% V_IN = 0V,
of Time)
Full Scale = 4V
-
2
-
-
2
-
µV
Leakage Current at Input (Note 14)
Zero Reading Drift
Scale Factor Temperature Coefficient
(Note 15)
V_IN = 0V
0V^oINC ^{=to07V0, o}C
0V^oINC ^{=to45V0, o}C
ext. ref. 0ppm/^oC
-
100
165
-
100
165
pA
-
0.5
-
-
0.5
-
µV/^oC
-
2
5
-
2
5
ppm/^oC
System Electrical Specifications: ICL8052/ICL7104 V++ = +15V, V+ = +5V, V- = -15V, f_CLOCK = 200kHz (Note 16)
PARAMETER
TEST
CONDITIONS
ICL8052A/ICL7104-14
MIN
TYP MAX
ICL8052A/ICL7104-16
MIN
TYP MAX
UNITS
Zero Input Reading
Ratiometric Error (Note 15)
Linearity Over ± Full Scale (Error of
Reading from Best Straight Line)
V_IN = 0V, V_REF = 2V
V_IN = V_REF = 2V
-4V ≤ V_IN ≤ +4V
-00000
-1
-
±00000 +00000
0
1
0.5
1
-00000
-1
-
±00000 +00000
0
1
0.5
1
Counts
LSB
LSB
Differential Linearity (Difference
-4V ≤ V_IN ≤ +4V
between Worst Case Step of Adjacent
Counts and Ideal Step)
-
0.01
-
-
0.01
-
LSB
Rollover Error (Difference in Reading
for Equal Positive and Negative
Voltage Near Full Scale)
-V_IN = +V_IN ≈ 4V
-
0.5
1
-
0.5
1
LSB
Noise (Peak-to-Peak Value Not
Exceeded 95% of Time)
V_IN = 0V,
Full Scale = 4V
-
30
-
-
30
-
µV
Leakage Current at Input (Note 14)
Zero Reading Drift
Scale Factor Temperature Coefficient
V_IN = 0V
0V^oINC ^{=to07V0, o}C
0V^oINC ^{=to45V0, o}C
ext. ref. 0ppm/^oC
-
20
30
-
20
30
pA
-
0.5
-
-
0.5
-
µV/^oC
-
2
-
-
2
-
ppm/^oC
NOTES:
13. Tested with low dielectric absorption integrating capacitor.
14. The input bias currents are junction leakage currents which approximately double for every 10^oC increase in the junction temperature,
T_J. Due to limited production test time, the input bias currents are measured with junctions at ambient temperature. In normal oper-
ation the junction temperature rises above the ambient temperature as a result of internal power dissipation, P_D. T_J = T_A + R_θJAP_D
where R_θJA is the thermal resistance from junction to ambient. A heat sink can be used to reduce temperature rise.
15. The temperature range can be extended to 70^oC and beyond if the Auto-Zero and Reference capacitors are increased to absorb the
high temperature leakage of the 8068. See note 14 above.
16. System Electrical Specifications are not tested; for reference only.
5-13