ICL8052 Datasheet, PDF (17/21 Pages) Intersil Corporation – 14-Bit/16-Bit, Microprocessor- Compatible, 2-Chip, A/D Converter

ICL8052/ICL7104, ICL8068/ICL7104
Entry into the handshake mode will occur if either of two
conditions are fulfilled; first, if new data is latched (i.e., a
conversion is completed) while MODE pin (pin 27) is high, in
which case entry occurs at the end of the latch cycle; or
secondly, if the MODE pin goes from low to high, when entry
will occur immediately (if new data is being latched, entry is
delayed to the end of the latch cycle). While in the
handshake mode, data latching is inhibited, and the MODE
pin is ignored. (Note that conversion cycles will continue in
the normal manner). This allows versatile initiation of hand-
shake operation without danger of false data generation; if
the MODE pin is held high, every conversion (other than
those completed during handshake operations) will start a
new handshake operation, while if the MODE pin is pulsed
high, handshake operations can be obtained “on demand.”
When the converter enters the handshake mode, or when
the MODE input is high, the chip and byte ENABLE termi-
nals become TTL-compatible outputs which provide the con-
trol signals for the output cycle. The Send ENABLE pin
(SEN) (pin 29) is used as an indication of the ability of the
external device to receive data. The condition of the line is
sensed once every clock pulse, and if it is high, the next (or
first) byte is enabled on the next rising CLOCK 1 (pin 25)
clock edge, the corresponding byte ENABLE line goes low,
and the CHIP ENABLE / LOAD pin (pin 30) (CE/LD) goes
low for one full clock pulse only, returning high.
On the next falling CLOCK 1 clock pulse edge, if SEN
remains high, or after it goes high again, the byte output
lines will be put in the high impedance state (or three-stated
off). One half pulse later, the byte ENABLE pin will be
cleared high, and (unless finished) the CE/LD and the next
byte ENABLE pin will go low. This will continue until all three
(2 in the case of the 14-bit device) bytes have been sent.
The bytes are individually put into the low impedance state
i.e.: three-stated on during most of the time that their byte
ENABLE pin is (active) low. When receipt of the last byte has
been acknowledged by a high SEN, the handshake mode
will be cleared, re-enabling data latching from conversion,
and recognizing the condition of the MODE pin again. The
byte and CHIP ENABLE will be three-stated off, if MODE is
low, but held by their (weak) pullups. These timing relation-
ships are illustrated in Figures 11, 12, and 13, and Table 2.
Figure 11 shows the sequence of the output cycle with SEN
held high. The handshake mode (Internal MODE high) is
entered after the data latch pulse (since MODE remains high
the CE/LD, LBEN, MBEN and HBEN terminals are active as
outputs). The high level at the SEN input is sensed on the
same high to low internal clock edge. On the next to high
internal clock edge, the CE/LD and the HBEN outputs
assume a low level and the high-order byte (POL and OR,
and except for -16, Bits 9 - 14) outputs are enabled. The
CE/LD output remains low for one full internal clock period
only, the data outputs remain active for 1¹/₂ internal clock
periods, and the high byte ENABLE remains low for two
clock periods. Thus the CE/LD output low level or low to high
edge may be used as a synchronizing signal to ensure valid
data, and the byte ENABLE as an output may be used as a
byte identification flag. With SEN remaining high the con-
verter completes the output cycle using CE/LD, MBEN and
LBEN while the remaining byte outputs (see Table 3) are
activated. The handshake mode is terminated when all bytes
are sent (3 for -16, 2 for -14).
Figure 12 shows an output sequence where the SEN input is
used to delay portions of the sequence, or handshake, to
ensure correct data transfer. This timing diagram shows the
relationships that occur using an industry-standard IM6402/3
CMOS UART to interface to serial data channels. In this
interface, the SEN input to the ICL7104 is driven by the
TBRE (Transmitter Buffer Register Empty) output of the
UART, and the CE/LD terminal of the ICL7104 drives the
TBRL (Transmitter Buffer Register Load) input to the UART.
The data outputs are paralleled into the eight Transmitter
Buffer Register inputs.
Assuming the UART Transmitter Buffer Register is empty,
the SEN input will be high when the handshake mode is
entered after new data is stored. The CE/LD and HBEN ter-
minals will go low after SEN is sensed, and the high order
byte outputs become active. When CE/LD goes high at the
end of one clock period, the high order byte data is clocked
into the UART Transmitter Buffer Register. The UART TBRE
output will now go low, which halts the output cycle with the
HBEN output low, and the high order byte outputs active.
When the UART has transferred the data to the Transmitter
Register and cleared the Transmitter Buffer Register, the
TBRE returns high. On the next ICL7104 internal clock high
to low edge, the high order byte outputs are disabled, and
one-half internal clock later, the HBEN output returns high.
At the same time, the CE/LD and MBEN (-16) or LBEN out-
puts go low, and the corresponding byte outputs become
active. Similarly, when the CE/LD returns high at the end of
one clock period, the enabled data is clocked into the UART
Transmitter Buffer Register, and TBRE again goes low.
When TBRE returns to a high it will be sensed on the next
ICL7104 internal clock high to low edge, disabling the data
outputs. For the 16-bit device, the sequence is repeated for
LBEN. One-half internal clock later, the handshake mode will
be cleared, and the chip and byte ENABLE terminals return
high and stay active (as long as MODE stays high).
With the MODE input remaining high as in these examples,
the converter will output the results of every conversion
except those completed during a handshake operation. By
triggering the converter into handshake mode with a low to
high edge on the MODE input, handshake output sequences
may be performed on demand. Figure 13 shows a
handshake output sequence triggered by such an edge. In
addition, the SEN input is shown as being low when the con-
verter enters handshake mode. In this case, the whole out-
put sequence is controlled by the SEN input, and the
sequence for the first (high order) byte is similar to the
sequence for the other bytes. This diagram also shows the
output sequence taking longer than a conversion cycle. Note
that the converter still makes conversions, with the STATUS
output and Run/Hold input functioning normally. The only
difference is that new data will not be latched when in
handshake mode, and is therefore lost.
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