ICL8052 Datasheet, PDF (15/21 Pages) Intersil Corporation – 14-Bit/16-Bit, Microprocessor- Compatible, 2-Chip, A/D Converter

ICL8052/ICL7104, ICL8068/ICL7104
Detailed Description
DIGITAL SECTION
The digital section includes the clock oscillator circuit, a
16-bit or 14-bit binary counter with output latches and TTL-
compatible three-state output drivers, polarity, over-range
and control logic and UART handshake logic, as shown in
the Block Diagram Figure 9 (16-bit version shown).
Throughout this description, logic levels will be referred to as
“low” or “high”. The actual logic levels are defined under
“ICL7104 Electrical Specification”. For minimum power con-
sumption, all inputs should swing from GND (low) to V+
(high). Inputs driven from TTL gates should have 3 - 5kΩ
pullup resistors added for maximum noise immunity.
MODE Input
The MODE input is used to control the output mode of the
converter. When the MODE pin is connected to GND or left
open (this input is provided with a pulldown resistor to
ensure a low level when the pin is left open), the converter is
in its “Direct” output mode, where the output data is directly
accessible under the control of the chip and byte enable
inputs. When the MODE input is pulsed high, the converter
enters the UART handshake mode and outputs the data in
three bytes for the 7104-16 or two bytes for the 7104-14 then
returns to “direct” mode. When the MODE input is left high,
the converter will output data in the handshake mode at the
end of every conversion cycle. (See section entitled “Hand-
shake Mode” for further details).
STATUS Output
During a conversion cycle, the STATUS output goes high at
the beginning of Input Integrate (Phase II), and goes low
one-half clock period after new data from the conversion has
been stored in the output latches. See Figure 8 for details of
this timing. This signal may be used as a “data valid” flag
(data never changes while STATUS is low) to drive inter-
rupts, or for monitoring the status of the converter.
TABLE 5. THREE-STATE BYTE FORMATS AND ENABLE PINS
CE/LD
HBEN
MBEN
LBEN
ICL7104-16 POL O/R B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1
HBEN
LBEN
ICL7104-14
POL O/R B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1
18/16 THREE-STATE OUTPUTS
18/16 LATCHES
INITIAL
CLEAR
18/16 BIT COUNTER
LATCH
CLOCK
TO
ANALOG
SECTION
COMP OUT
AZ
INT
DEINT(+)
DEINT(-)
CONVERSION
CONTROL
LOGIC
2
STATUS
26
R/H
OSCILLATOR
AND CLOCK
CIRCUITRY
24
23
25
CLOCK CLOCK CLOCK
(1)
(2)
(3)
HANDSHAKE
LOGIC
21
MODE
27
SEND
FIGURE 9. DIGITAL SECTION
HBEN
MBEN
(-16 ONLY)
LBEN
CE/LD
5-20