ICL8052 Datasheet, PDF (10/21 Pages) Intersil Corporation – 14-Bit/16-Bit, Microprocessor- Compatible, 2-Chip, A/D Converter

SYMBOL
t_BEA
t_DAB
t_DHB
t_CEA
t_DAC
t_DHC
t_CWH
ICL8052/ICL7104, ICL8068/ICL7104
TABLE 1. DIRECT MODE TIMING REQUIREMENTS (Note: Not tested in production)
DESCRIPTION
MIN
TYP
MAX
XBEN (Min) Pulse Width.
-
300
-
Data Access Time from XBEN.
-
300
-
Data Hold Time from XBEN.
-
200
-
CE/LD Min. Pulse Width.
-
350
-
Data Access Time from CE/LD.
-
350
-
Data Hold Time from CE/LD.
-
280
-
CLOCK 1 High Time.
-
1000
-
SYMBOL
t_MW
t_SM
t_ME
t_MB
t_CEL
t_CEH
t_CBL
t_CBH
t_CDH
t_CDL
t_SS
t_CBZ
t_CEZ
t_CWH
TABLE 2. HANDSHAKE TIMING REQUIREMENTS (Note: Not tested in production)
DESCRIPTION
MIN
TYP
MAX
Mode Pulse (Min).
-
20
-
Mode Pin Set-Up Time.
-
-150
-
Mode Pin High to Low Z CE/LD High Delay.
-
200
-
Mode Pin High to XBEN Low Z (High) Delay.
-
200
-
Clock 1 High to CE/LD Low Delay.
-
700
-
Clock 1 High to CE/LD High Delay.
-
600
-
Clock 1 High to XBEN Low Delay.
-
900
-
Clock 1 High to XBEN High Delay.
-
700
-
Clock 1 High to Data Enabled Delay.
-
1100
-
Clock 1 Low to Data Disabled Delay.
-
1100
-
Send ENABLE Set-Up Time.
-
-350
-
Clock 1 High to XBEN Disabled Delay.
-
2000
-
Clock 1 High to CE/LD Disabled Delay.
-
2000
-
Clock 1 High Time.
1250
1000
-
UNIT
ns
ns
ns
ns
ns
ns
ns
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5-15