ICL8052 Datasheet, PDF(11/21 Page) Intersil Corporation – 14-Bit/16-Bit, Microprocessor- Compatible, 2-Chip, A/D Converter

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ICL8052 Datasheet, PDF (11/21 Pages) Intersil Corporation – 14-Bit/16-Bit, Microprocessor- Compatible, 2-Chip, A/D Converter

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ICL8052/ICL7104, ICL8068/ICL7104

CLOCK 1 H

(PIN 25) L

tCWH

EITHER: H

tMW

MODE PIN L

INTERNAL

LATCH PULSE IF

MODE âHIâ

INTERNAL UART

MODE NORM

CE/LD L

tCEL

tME

SEN

(EXTERNAL

SIGNAL)

HBEN

DONâT CARE

tMB

O/R, POL H

01-14 L

LBEN L

tSM

IGNORED

tCEH

EXT

tCBL

DATA VALID, STABLE

tCDH

DONâT CARE

IGNORED

tSS

tCBH

tCDL

STABLE

tCEZ

tCBZ

DONâT CARE

BITS 1-5

HANDSHAKE MODE

TRIGGERED BY

DATA VALID, STABLE

THREE-STATE

-16 HAS EXTRA (MBEN) PHASE

FIGURE 5. HANDSHAKE MODE TIMING DIAGRAM

THREE-STATE WITH PULLUP

Detailed Description

ANALOG SECTION

Figure 6 shows the equivalent Circuit of the Analog Section

of both the ICL7104/8052 and the ICL7104/8068 in the 3

different phases of operation. If the Run/Hold pin is left open

or tied to V+, the system will perform conversions at a rate

determined by the clock frequency: 131,072 for - 16 and

32,368 for - 14 clock periods per cycle (see Figure 8

conversion timing).

Auto-Zero Phase I (Figure 6A)

During Auto-Zero, the input of the buffer is shorted to analog

ground thru switch 2, and switch 1 closes a loop around the

integrator and comparator. The purpose of the loop is to

charge the Auto-Zero capacitor until the integrator output no

longer changes with time. Also, switches 4 and 9 recharge

the reference capacitor to VREF.

Input Integrate Phase II (Figure 6B)

During input integrate the Auto-Zero loop is opened and the

analog input is connected to the buffer input thru switch 3.

(The reference capacitor is still being charged to VREF

during this time.) If the input signal is zero, the buffer,

integrator and comparator will see the same voltage that

existed in the previous sate (Auto-Zero). Thus the integrator

output will not change but will remain stationary during the

entire Input Integrate cycle. If VIN is not equal to zero, an

unbalanced condition exists compared to the Auto-Zero

phase, and the integrator will generate a ramp whose slope

is proportional to VIN. At the end of this phase, the sign of

the ramp is latched into the polarity F/F.

Deintegrate Phase III (Figures 6C and 6D)

During the Deintegrate phase, the switch drive logic uses the

output of the polarity F/F in determining whether to close

switches 6 and 9 or 7 and 8. If the input signal was positive,

switches 7 and 8 are closed and a voltage which is VREF

more negative than during Auto-Zero is impressed on the

buffer input. Negative inputs will cause +VREF to be applied

to the buffer input via switches 6 and 9. Thus, the reference

capacitor generates the equivalent of a (+) reference or a (-)

reference from the single reference voltage with negligible

error. The reference voltage returns the output of the integra-

tor to the zero-crossing point established in Phase I. The

time, or number of counts, required to do this is proportional

to the input voltage. Since the Deintegrate phase can be

twice as long as the Input integrate phase, the input voltage

required to give a full scale reading = 2VREF.

NOTE: Once a zero crossing is detected, the system automatically

reverts to Auto-Zero phase for the leftover Deintegrate time (unless

RUN/HOLD is manipulated, see RUN/HOLD input in detailed

description, digital section).

5-16

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