82C59A_06 Datasheet, PDF (8/22 Pages) Intersil Corporation – CMOS Priority Interrupt Controller

82C59A
When interval = 4 bits, A5 - A7 are programmed, while
A0 - A4 are automatically inserted by the 82C59A. When
interval = 8, only A6 and A7 are programmed, while A0 - A5
are automatically inserted.
CONTENT OF SECOND INTERRUPT VECTOR BYTE
IR
INTERVAL = 4
D7 D6 D5 D4 D3 D2 D1 D0
7 A7 A6 A5 1
1
1
0
0
6 A7 A6 A5 1
1
0
0
0
5 A7 A6 A5 1
0
1
0
0
4 A7 A6 A5 1
0
0
0
0
3 A7 A6 A5 0
1
1
0
0
2 A7 A6 A5 0
1
0
0
0
1 A7 A6 A5 0
0
1
0
0
0 A7 A6 A5 0
0
0
0
0
IR
INTERVAL = 8
D7 D6 DS D4 D3 D2 D1 D0
7 A7 A6 1
1
1
0
0
0
6 A7 A6 1
1
0
0
0
0
5 A7 A6 1
0
1
0
0
0
4 A7 A6 1
0
0
0
0
0
3 A7 A6 0
1
1
0
0
0
2 A7 A6 0
1
0
0
0
0
1 A7 A6 0
0
1
0
0
0
0 A7 A6 0
0
0
0
0
0
During the third INTA pulse, the higher address of the
appropriate service routine, which was programmed as byte 2
of the initialization sequence (A8 - A15), is enabled onto the
bus.
CONTENT OF THIRD INTERRUPT VECTOR BYTE
D7 D6 D5 D4 D3 D2 D1 D0
A15 A14 A13 A12 A11 A10 A9 A8
80C86, 8OC88, 80C286 Interrupt Response Mode
80C86/88/286 mode is similar to 8080/85 mode except that
only two Interrupt Acknowledge cycles are issued by the
processor and no CALL opcode is sent to the processor. The
first interrupt acknowledge cycle is similar to that of 8080/85
systems in that the 82C59A uses it to internally freeze the
state of the interrupts for priority resolution and, as a master,
it issues the interrupt code on the cascade lines. On this first
cycle, it does not issue any data to the processor and leaves
its data bus buffers disabled. On the second interrupt
acknowledge cycle in the 86/88/286 mode, the master (or
slave if so programmed) will send a byte of data to the
processor with the acknowledged interrupt code composed
as follows (note the state of the ADI mode control is ignored
and A5 - A11 are unused in the 86/88/286 mode).
CONTENT OF INTERRUPT VECTOR BYTE FOR
80C86/88/286 SYSTEM MODE
D7 D6 D5 D4 D3 D2 D1 D0
lR7 T7 T6 T5 T4 T3 1
1
1
lR6 T7 T6 T5 T4 T3 1
1
0
IR5 T7 T6 T5 T4 T3 1
0
1
IR4 T7 T6 T5 T4 T3 1
0
0
IR3 T7 T6 T5 T4 T3 0
1
1
IR2 T7 T6 T5 T4 T3 0
1
0
IR1 T7 T6 T5 T4 T3 0
0
1
IR0 T7 T6 T5 T4 T3 0
0
0
Programming the 82C59A
The 82C59A accepts two types of command words
generated by the CPU:
1. Initialization Command Words (ICWs): Before normal
operation can begin, each 82C59A in the system must be
brought to a starting point - by a sequence of 2 to 4 bytes
timed by WR pulses.
2. Operation Command Words (OCWs): These are the
command words which command the 82C59A to operate
in various interrupt modes. Among these modes are:
a. Fully nested mode.
b. Rotating priority mode.
c. Special mask mode.
d. Polled mode.
The OCWs can be written into the 82C59A anytime after
initialization.
Initialization Command Words (lCWs)
General
Whenever a command is issued with A0 = 0 and D4 = 1, this
is interpreted as Initialization Command Word 1 (lCW1).
lCW1 starts the initialization sequence during which the
following automatically occur:
a. The edge sense circuit is reset, which means that follow-
ing initialization, an interrupt request (IR) input must make
a low-to-high transition to generate an interrupt.
b. The Interrupt Mask Register is cleared.
c. lR7 input is assigned priority 7.
d. Special Mask Mode is cleared and Status Read is set to
lRR.
8
FN2784.5
March 17, 2006