82C59A_06 Datasheet, PDF (18/22 Pages) Intersil Corporation – CMOS Priority Interrupt Controller

82C59A
AC Electrical Specifications V_CC = +5.0V ±10%, GND = 0V, T_A = Operating Temperature Range (Continued)
SYMBOL
PARAMETER
5MHz
MIN MAX
8MHz
MIN MAX
12.5MHz
MIN MAX
UNITS
TEST
CONDITIONS
(4) TAHWL A0/CS Setup to WR
0
-
0
-
0
-
ns
(5) TWHAX A0/CS Hold after WR
5
-
5
-
0
-
ns
(6) TWLWH WR Pulse Width
165
-
95
-
60
-
ns
(7) TDVWH Data Setup to WR
240
-
160
-
70
-
ns
(8) TWHDX Data Hold after WR
5
-
5
-
0
-
ns
(9) TJLJH Interrupt Request Width Low
100
-
100
-
40
-
ns
(10) TCVlAL Cascade Setup to Second or Third INTA (Slave 55
-
40
-
30
-
ns
Only)
(11) TRHRL End of RD to next RD, End of INTA (within an
160
-
160
-
90
-
ns
INTA sequence only)
(12) TWHWL End of WR to next WR
190
-
190
-
60
-
ns
(13) TCHCL End of Command to next command (not same 500
-
400
-
90
-
ns
(Note 1)
command type), End of INTA
sequence to next INTA sequence
TIMING RESPONSES
(14) TRLDV Data Valid from RD/INTA
-
160
-
120
-
40
ns
1
(15) TRHDZ Data Float after RD/INTA
5 100 5
85
5
22
ns
2
(16) TJHlH Interrupt Output Delay
-
350
-
300
-
90
ns
1
(17) TlALCV Cascade Valid from First INTA
(Master Only)
-
565
-
360
-
50
ns
1
(18) TRLEL Enable Active from RD or INTA
-
125
-
100
-
40
ns
1
(19) TRHEH Enable Inactive from RD or INTA
-
60
-
50
-
22
ns
1
(20) TAHDV Data Valid from Stable Address
-
210
-
200
-
60
ns
1
(21) TCVDV Cascade Valid to Valid Data
-
300
-
200
-
70
ns
1
NOTE:
1. Worst case timing for TCHCL in an actual microprocessor system is typically greater than the values specified for the 82C59A,
(i.e. 8085A = 1.6µs, 8085A -2 = 1µs, 80C86 = 1µs, 80C286 -10 = 131ns, 80C286 -12 = 98ns).
AC Test Circuit
V₁
OUTPUT FROM
DEVICE UNDER
TEST
C₁
(NOTE)
R₁
TEST
POINT
R₂
NOTE: Includes stray and jig capacitance.
TEST CONDITION DEFINITION TABLE
TEST
CONDITION
1
V₁
1.7V
R₁
523Ω
R₂
Open
C₁
100pF
2
V_CC
1.8kΩ 1.8kΩ 50pF
18
FN2784.5
March 17, 2006