82C59A_06 Datasheet, PDF (3/22 Pages) Intersil Corporation – CMOS Priority Interrupt Controller

Pinouts
82C59A (PDIP, CERDIP)
TOP VIEW
CS 1
WR 2
RD ³
D7 4
D6 5
D5 6
D4 7
D3 8
D2 9
D1 10
D0 11
CAS 0 12
CAS 1 13
GND 14
28 V_CC
27 A0
26 INTA
25 IR7
24 IR6
23 IR5
22 IR4
21 IR3
20 IR2
19 IR1
18 IR0
17 INT
16 SP/EN
15 CAS 2
82C59A
82C59A (PLCC, CLCC)
TOP VIEW
4 3 2 1 28 27 26
D6 5
25 IR7
D5 6
24 IR6
D4 7
23 IR5
D3 8
22 IR4
D2 9
21 IR3
D1 10
20 IR2
D0 11
19 IR1
12 13 14 15 16 17 18
PIN
D7 - D0
RD
WR
A0
CS
CAS 2 - CAS 0
SP/EN
INT
INTA
IR0 - IR7
DESCRIPTION
Data Bus (Bidirectional)
Read Input
Write Input
Command Select Address
Chip Select
Cascade Lines
Slave Program Input Enable
Interrupt Output
Interrupt Acknowledge Input
Interrupt Request Inputs
Functional Diagram
INTA
INT
D₇-D₀
DATA
BUS
BUFFER
CONTROL LOGIC
RD
WR
A₀
CS
CAS 0
CAS 1
CAS 2
SP/EN
READ/
WRITE
LOGIC
CASCADE
BUFFER
COMPARATOR
IN -
SERVICE
REG
(ISR)
PRIORITY
RESOLVER
IR0
IR1
INTERRUPT
IR2
REQUEST
IR3
REG
IR4
(IRR)
IR5
IR6
IR7
INTERRUPT MASK REG
(IMR)
INTERNAL BUS
FIGURE 1.
3
FN2784.5
March 17, 2006