82C59A_06 Datasheet, PDF (20/22 Pages) Intersil Corporation – CMOS Priority Interrupt Controller

Timing Waveforms (Continued)
82C59A
(16)
TJHIH
IR
(9)
TJLJH
INT
INTA
SEE NOTE 1
SEE NOTE 3 SEE NOTE 4
DB
CAS 0 - 2
SEE
NOTE 2
(10)
TCVIAL
(17)
(21)
TIALCV TCVDV
(10)
TCVIAL
NOTES:
1. Interrupt Request (IR) must remain HIGH until leading edge of first INTA.
2. During first INTA the Data Bus is not active in 80C86/88/286 mode.
3. 80C86/88/286 mode.
4. 8080/8085 mode.
FIGURE 15. INTA SEQUENCE
Burn-In Circuits
MD82C59A CERDIP
GND
WR
RD
D7
D6
D5
D4
D3
D2
D1
D0
CAS 0
CAS 1
GND
R1 ₁
R1 ₂
R1 ₃
R1 ₄
R1 ₅
R1 ₆
R1 ₇
R1 ₈
R1 ₉
R1 ₁₀
R1 ₁₁
R3 ₁₂
R3 ₁₃
14
28
27 ^R1
26 ^R1
25 ^R2
24 ^R2
23 ^R2
22 ^R2
21 ^R2
20 ^R2
19 ^R2
18 ^R2
17
16 ^R3
15 ^R3
V_CC
A0
C1
INTA
IR7
IR6
V_CC
IR5
IR4
R3
IR3
A
IR2
IR1
R3
IR0
A
SP/EN
CAS 2
20
FN2784.5
March 17, 2006