X9440 Datasheet, PDF (7/21 Pages) Intersil Corporation – Mixed Signal with SPI Interface

X9440
Figure 6. Three-Byte Command Sequence (Read)
CS
SCL
SI
0 1 0 1 0 0 A1 A0
I3 I2 I1 I0 R1 R0 P1 P0
S0
Figure 7. Increment/Decrement Command Sequence
CS
SCK
Don’t Care
0 0 D5 D4 D3 D2 D1 D0
SI
0 1 0 1 0 0 A1 A0
I3 I2 I1 I0 0 0 P1 P0
II
ID
D
NN
NE
E
CC
CC
C
12
n1
n
Increment/Decrement
The final command is Increment/Decrement. It is differ-
ent from the other commands, because it’s length is
indeterminate. Once the command is issued, the mas-
ter can clock the selected wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning
capability to the host. For each SCK clock pulse (t_HIGH)
while SI is HIGH, the selected wiper will move one
resistor segment towards the V_H terminal. Similarly, for
each SCK clock pulse while SI is LOW, the selected
Figure 8. Increment/Decrement Timing Limits
SCK
wiper will move one resistor segment towards the V_L
terminal. A detailed illustration of the sequence and tim-
ing for this operation are shown in Figure 7 and 8.
Write in Process
The contents of the data registers are saved to nonvol-
atile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write opera-
tion can be monitored by a write in process bit (WIP).
The WIP bit is read with a read status command.
t_WRID
SI
V_W
Voltage Out
INC/DEC CMD Issued
7
FN8200.0
March 28, 2005