X9440 Datasheet, PDF (4/21 Pages) Intersil Corporation – Mixed Signal with SPI Interface

X9440
REGISTERS
Both digitally-controlled potentiometers and voltage com-
parators share the serial interface and share a common
architecture. Each potentiometer and voltage comparator
is associated with wiper counter and analog control reg-
isters and eight data registers. A detailed discussion of
the register organization and array operation follows.
Wiper Counter (WCR) and Analog Control
Registers (ACR)
The X9440 contains two wiper counter registers: one
for each XDCP potentiometer and two Analog Control
Registers, and one for each of the two voltage com-
parators. The wiper counter register is equivalent to a
serial-in, parallel-out counter with its outputs decoded
to select one of sixty-four switches along its resistor
array. The contents of the wiper counter register and
analog control register can be altered in four ways: it
may be written directly by the host via the Write WCR
instruction (serial load); it may be written indirectly by
transferring the contents of one of four associated
data registers (DR) via the XFR data register instruc-
tion (parallel load); it can be modified one step at a
time by the increment/ decrement instruction (WCR
only). Finally, it is loaded with the contents of its data
register zero (R0) upon power-up.
The wiper counter and analog control register are vol-
atile registers; that is, their contents are lost when the
X9440 is powered-down. Although the registers are
automatically loaded with the value in R0 upon power-
up, it should be noted this may be different from the
value present at power-down.
Programming the ACR is similar to the WCR. How-
ever, the 6 bits in the WCR positions the wiper in the
resistor array while 3 bits in the ACR control the com-
parator and its output.
Data Registers (DR)
Each potentiometer and each voltage comparator has
four non volatile data registers (DR). These can be
read or written directly by the host and data can be
transferred between any of the four data registers and
the WCR or ACR. It should be noted all operations
changing data in one of these registers is a non vola-
tile operation and will take a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer or comparator, these reg-
isters can be used as regular memory locations that
could store system parameters or user preference data.
Figure 1. Detailed Potentiometer Block Diagram
(One of Two Arrays)
Serial Data Path
Serial
V_H
From Interface
Circuitry
Bus
Input
C
Register 0
Register 1
o
u
8
6 Parallel
Bus
Input
n
t
e
r
Register 2
Register 3
Wiper
D
Counter _e
Register c
(WCR) o
d
e
Inc/Dec
If WC = 00[H] V_W = V_L
If WC = 3F[H] V_W = V_H
UP/DN
Modified SCK
Logic
UP/DN
CLK
V_L
V_W
4
FN8200.0
March 28, 2005