X9440 Datasheet, PDF (6/21 Pages) Intersil Corporation – Mixed Signal with SPI Interface

X9440
Four of the ten instructions end with the transmission
of the instruction byte. The basic sequence is illus-
trated in Figure 4. These two-byte instructions
exchange data between the wiper counter register or
analog control register and one of the data registers. A
transfer from a data register to a wiper counter register
or analog control register is essentially a write to a
static RAM. The response of the wiper to this action
will be delayed t_WRL. A transfer from the wiper counter
register current wiper position to a data register is a
write to non volatile memory and takes a minimum of
t_WR to complete. The transfer can occur between one
of the two potentiometers or one of the two voltage
comparators and one of its associated registers; or it
may occur globally, wherein the transfer occurs
between both of the potentiometers and voltage com-
parators and one of their associated registers.
Figure 4. Two-Byte Command Sequence
Five instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9440; either between the host and
one of the data registers or directly between the host
and the wiper counter and analog control registers.
These instructions are: Read Wiper Counter Register
or Analog Control Register, read the current wiper
position of the selected pot or the comparator control
bits, Write Wiper Counter Register or Analog Control
Register, i.e. change current wiper position of the
selected pot or control the voltage comparator; Read
Data Register, read the contents of the selected non
volatile register; Write Data Register, write a new value
to the selected data register. The bit structures of the
instructions are shown in Figure 9.
The sequences of the three byte operations are shown
in Figure 5 and Figure 6.
The bit structures of the instructions and the descrip-
tion of the instructions are shown in Figure 10.
CS
SCK
SI
0 1 0 1 0 0 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0
Figure 5. Three-Byte Command Sequence (Write)
CS
SCL
SI
0 1 0 1 0 0 A1 A0
I3 I2 I1 I0 R1 R0 P1 P0
0 0 D5 D4 D3 D2 D1 D0
6
FN8200.0
March 28, 2005