X9440 Datasheet, PDF (5/21 Pages) Intersil Corporation – Mixed Signal with SPI Interface

X9440
REGISTER BIT DESCRIPTIONS
Wiper Counter Register (WCR)
0 0 WP5 WP4 WP3 WP2 WP1 WP0
(volatile)
(LSB)
WP0-WP5 identify wiper position.
Analog Control Register (ACR)
User- User- User-
Shut-
0 0 bit5 bit4 bit3 Latch Enable down
(volatile)
(LSB)
Shutdown
“1” indicates power is connected to the voltage
comparator.
“0” indicates power is not connected to the voltage
comparator.
Enable
“1” indicates the output buffer of the voltage
comparator is enabled.
“0” indicates the output buffer of the voltage
comparator is disabled.
Latch
“1” indicates the output of the voltage comparator is
memorized or latched.
“0” indicates the output of the voltage comparator is
not latched.
Userbits—available for user applications
Data Registers (DR, R₀-R₃)
Wiper Position or Analog Control Data or User Data
(Nonvolatile)
{Refer to Memory Map, Figure 9}
INSTRUCTIONS AND PROGRAMMING
Identification (ID) Byte
The first byte sent to the X9440 from the host, follow-
ing a CS going HIGH to LOW, is called the Identifica-
tion byte. The most significant four bits of the slave
address are a device type identifier, for the X9440 this
is fixed as 0101[B] (refer to Figure 2).
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A₀-A₁ input pins.
The X9440 compares the serial data stream with the
address input state; a successful compare of both
address bits is required for the X9440 to successfully
continue the command sequence. The A₀-A₁ inputs
can be actively driven by CMOS input signals or tied to
V_CC or V_SS.
The remaining two bits in the slave byte must be set to 0.
Figure 2. Identification Byte Format
Device Type
Identifier
0 1 0 1 _{0 0 A1 A0}
Device Address
Instruction Byte
The byte following the address contains the instruction
and register pointer information. The four most signifi-
cant bits are the instruction. The next four bits point to
one of the two pots or two voltage comparators and
when applicable they point to one of four associated
registers. The format is shown below in Figure 3.
Figure 3. Instruction Byte Format
Register
Select
I3 I2 I1 I0 R1 R0 P1 P0
Instructions
Pot Select
The four high order bits of the instruction byte specify
the operation. The next two bits (R₁ and R₀) select one
of the four data registers that is to be acted upon when
a register oriented instruction is issued. The last two
bits (P₁ and P₀) selects which one of the four potenti-
ometers is to be affected by the instruction.
The four high order bits define the instruction. The next
two bits (R₁ and R₀) select one of the four data registers
that is to be acted upon when a register oriented instruc-
tion is issued. The last two bits (P₁ and P₀) select which
one of the two potentiometers or which one of the two
voltage comparators is to be affected by the instruction.
5
FN8200.0
March 28, 2005