ISL33001 Datasheet, PDF (7/19 Pages) Intersil Corporation – I2C Bus Buffer with Rise Time Accelerators and Hot Swap Capability

ISL33001, ISL33002, ISL33003
Test Circuits and Waveforms
- SDA and SCL pins connected to V_CC
- Enable Delay Time Measured on ISL33001 only
- ISL33003 performance inferred from ISL33001
V_CC
V_EN
0V
V_CC
0V
V_READY
0.5 * V_CC
0.5 * V_CC
- V_{SDA_IN} = V_{SDA_OUT} = V_{SCL_OUT} = V_EN = V_CC
- EN Logic High for t > Enable Delay, t_{EN_LH}
prior to SCL_IN transition
- Bus Idle Time Measured on ISL33001 only
- ISL33002 and ISL33003 performance
inferred from ISL33001
V_CC
V_{SCL_IN}
0V
0.5V_CC
V_CC
V_READY
0V
0.5V_CC
t_EN-LH
FIGURE 1. ENABLE DELAY TIME
t_IDLE
FIGURE 2. BUS IDLE TIME
+3.3V
10kΩ
SCL_OUT
10kΩ
SCL_IN
V_IN
0.2V
V_CC1
10kΩ
SDA_OUT
10kΩ
GND
SDA_IN
V_IN
0.2V
0.2V
SCL_IN OR
SDA_IN
SCL_OUT OR ^VO
SDA_OUT
V_OS = V_O - 0.2V
FIGURE 3A. TEST CIRCUIT
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. INPUT TO OUTPUT OFFSET VOLTAGE
+2.7V
900Ω
SCL_OUT
900Ω
SCL_IN
0V
V_CC1
900Ω
SDA_OUT
GND
SDA_IN
0V
900Ω
SCL_OUT
V_OL
SDA_OUT
V_OL
V_CC1
V_CC1
FIGURE 4A. TEST CIRCUIT
FIGURE 4B. MEASUREMENT POINTS
FIGURE 4. OUTPUT LOW VOLTAGE
7
FN7560.2
September 30, 2010