ISL33001 Datasheet, PDF (11/19 Pages) Intersil Corporation – I2C Bus Buffer with Rise Time Accelerators and Hot Swap Capability

ISL33001, ISL33002, ISL33003
to perform level shifting with the V_CC1 and V_CC2 supplies
and provide capacitance buffering.
Propagation Delays
On a low to high transition, the rising edge signal is
determined by the bus pull-up resistor, load capacitance,
and the accelerator current from the ISL33001,
ISL33002, ISL33003 buffer. Prior to the accelerators
becoming active, the buffer is connected and the output
voltage will track the input of the buffer. When the
accelerators activate the buffer connection is released
and the signal on each side of the buffer rises
independently. The accelerator current on both sides of
the buffer will be equal. If the pull-up resistance on both
sides of the buffer are also equal, then differences in the
rise time will be proportional to the difference in
capacitive loading on the two sides.
Because the signals on each side of the buffer rise
independently, the propagation delay can be positive or
negative. If the input side rises slowly relative to the
output (i.e., heavy capacitive loading on the input and
light load on the output) then the propagation delay t_PLH
is negative. If the output side rises slowly relative to the
input, t_PLH is positive.
For high to low transitions, there is a finite propagation
delay through the buffer from the time an external low
on the input drives the NMOS output low. This
propagation delay will always be positive because the
buffer connect threshold on the falling edge is below the
measurement points of the delay. In addition to the
propagation delay of the buffer, there will be additional
delay from the different capacitive loading of the buffer.
Figures 21 and 22 show how the propagation delay from
high to low, t_PHL, is affected by V_CC and capacitive
loading.
The buffer’s propagation delay times for rising and falling
edge signals must be taken into consideration for the
timing requirements of the system. SETUP and HOLD
times may need to be adjusted to take into account
excessively long propagation delay times caused by
heavy bus capacitances.
Pull-Up Resistor Selection
While the ISL33001, ISL33002, ISL33003 2-Channel
buffers are designed to improve the rise time of the bus
in passive pull-up systems, proper selection of the
pull-up resistor is critical for system operation when a
buffer is used. For a bus that is operating normally
without active rise time circuitry, using the ISL33001,
ISL33002, ISL33003 buffer will allow larger pull-up
resistor values to reduce sink currents when the bus is
driving low. However, choose a pull-up resistor value of
no larger than 20kΩ regardless of the bus capacitance
seen on the SDA/SCL lines. The Bus Idle or Stop Bit
condition requires valid logic high voltages to give a valid
connection state. Pull-up resistor values 20kΩ or smaller
are recommended to overcome the typical 150kΩ
impedance of the pre-charge circuitry, delivering valid
high levels.
Typical Performance Curves C_IN = C_OUT = 10pF, V_CC1 = V_CC2 = V_CC, T_A = +25°C; Unless Otherwise
Specified.
2.4
2.3
T = -40°C
2.2
2.1
T = +25°C
2.0
T = +85°C
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
V_CC1 (V)
FIGURE 9. I_CC1 ENABLED CURRENT vs V_CC1
(ISL33001)
600
550
500
450
T = +25°C
400
T = +85°C
350
300
250
200
150
100
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
V_CC1 (V)
FIGURE 10. I_CC1 DISABLED CURRENT vs V_CC1
(ISL33001)
11
FN7560.2
September 30, 2010