ISL33001 Datasheet, PDF (3/19 Pages) Intersil Corporation – I2C Bus Buffer with Rise Time Accelerators and Hot Swap Capability

ISL33001, ISL33002, ISL33003
Pin Configurations (Continued)
ISL33002
(8 LD TDFN)
TOP VIEW
ISL33002
(8 LD MSOP)
TOP VIEW
V_{CC2 1}
SCL_OUT 2
SCL_IN 3
GND 4
PAD
8 VCC1
7 SDA_OUT
6 SDA_IN
5 ACC
V_{CC2 1}
SCL_OUT 2
SCL_IN 3
GND 4
8 ^VCC1
7 SDA_OUT
6 SDA_IN
5 ACC
ISL33003
(8 LD TDFN)
TOP VIEW
V_{CC2 1}
SCL_OUT ₂
SCL_IN 3
GND 4
PAD
8 VCC1
7 SDA_OUT
6 SDA_IN
5 EN
ISL33003
(8 LD MSOP)
TOP VIEW
V_{CC2 1}
SCL_OUT 2
SCL_IN 3
GND 4
8 ^VCC1
7 SDA_OUT
6 SDA_IN
5 EN
Pin Descriptions
NAME
NOTES
PIN NUMBER
FUNCTION
V_CC1
8
V_CC1 power supply, +2.3V to +5.5V. Decouple V_CC1 to ground with a high
frequency 0.01µF to 0.1µF capacitor.
V_CC2
ISL33002, ISL33003
GND
1
V_CC2 power supply, +2.3V to +5.5V. Decouple V_CC2 to ground with a high
frequency 0.01µF to 0.1µF capacitor. In level shifting applications, SDA_OUT
and SCL_OUT logic thresholds are referenced to V_CC2 supply levels. Connect
pull-up resistors on these pins to V_CC2.
4
Device Ground Pin
EN
ISL33001
ISL33003
1
Buffer Enable Pin. Logic “0” disables the device. Logic “1” enables the
5
device. Logic threshold referenced to V_CC1.
READY
ISL33001 only
5
Buffer Active ‘Ready’ Logic Output. When buffer is active, READY is high
impedance. When buffer is inactive, READY is low impedance to ground.
ACC
SDA_IN
ISL33002 only
5
Rise Time Accelerator Enable Pin. Logic “0” disables the accelerator. Logic
“1” enables the accelerator. Logic threshold referenced to V_CC1.
6
Data I/O Pins
SDA_OUT
7
SCL_IN
3
Clock I/O Pins
SCL_OUT
2
PAD Thermal Pad; TDFN only
Thermal pad should be connected to ground or float.
3
FN7560.2
September 30, 2010