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ISL5216 Datasheet, PDF (51/65 Pages) Intersil Corporation – Four-Channel Programmable Digital DownConverter | |||
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ISL5216
Electrical Speciï¬cations TVACC=1-4=0CoCorteoS8u5popClyI:n2d.u5sVtr±ia0l .1(2C5oVn,tVinCuCe2d)= I/O Supply: 3.3 ± 0.165V ,
PARAMETER
SYMBOL
MIN
MAX
UNITS
R/W Hold Time from Rising Edge of DSTRB
SERIAL CLOCK OUTPUT TIMING (FIGURE 11)
tR/WHR
0
-
ns
CLK to Serial Data, Sync and SCLK (Divide-by 2 thru 16 Modes)
tPD
-
8
ns
CLK to SCLK (Divide-by 1 Mode, Note 25)
tPDL
-
6.5
ns
Time Skew Between SCLK and Serial Data or Serial Sync (Divide-by 2 thru 16 Modes, Note 25) tSKEW1
-2
2
ns
Time Skew Between SCLK and Serial Data or Serial Sync (Divide-by 1 Mode, Note 25)
tSKEW2
1
3
ns
NOTES:
24. The ISL5216 goes into reset immediately on RESET going low and comes out of reset on the 4th rising edge of CLK after RESET goes high.
25. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes.
AC Test Load Circuit
DUT
S1
CL (NOTE)
NOTE - TEST HEAD CAPACITANCE, 40pF (TYP)
SWITCH S1 OPEN FOR ICCSB AND ICCOP
±
IOH
1.5V
IOL
EQUIVALENT CIRCUIT
Waveforms
CLK
AIN, BIN, CIN, DIN, ENIA,
ENIB, ENIC, ENID, SYNCI,
SYNCI(0-3)
SYNCO, INTRPT
RESET
1/fCLK
tCH
tCL
tDS
tDH
tPDC
tRW
tRS
FIGURE 6. INPUT AND CONTROL TIMING
51
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