ISL5216 Datasheet, PDF (36/65 Pages) Intersil Corporation – Four-Channel Programmable Digital DownConverter

ISL5216
P(15:0)
15:0
TABLE 7. CIC DECIMATION FACTOR REGISTER (IWA = *002h)
FUNCTION
Load with the desired CIC decimation factor minus 1.
P(15:0)
15:6
5:1
0
TABLE 8. CIC DESTINATION FIR AND OUTPUT ENABLE/DISABLE REGISTER (IWA = *003h)
FUNCTION
Set to zero.
CIC output destination (FIR # in FIR processor). Usually set to 00001.
CIC output enable. Active high. When low, the data writes from the CIC to the filter compute engine are inhibited.
P(31:0)
31:20
19:14
13:9
8:6
5
4
3
2:1
0
TABLE 9. CARRIER NCO/CIC CONTROL REGISTER (IWA = *004h)
FUNCTION
Reserved, set to zero.
CIC barrel shift control.
000000 is the minimum shift factor and 101111 (47 decimal) is maximum shift factor. 000000 = Shift Factor of 0; 011111 = Shift Factor
of 31; 100000 = Shift Factor of 32; 101111 = Shift Factor of 47. This compensates for the CIC filter gain of R^N, where N is the number
of enabled CIC stages and R is the CIC decimation factor. The equation used to compute the shift factor is:
Shift Factor = 45 - Ceiling(log₂(R^N)). Use a shift of 45 decimal when bypassing the CIC. Note that shifts of 46 and 47 may cause loss
of MSBs.
Examples:
N
R
5
512
5
8
Shift Factor
0
30
CIC stage bypasses. The integrator/comb pairs are numbered 1 thru 5, with 1 being the first integrator and first comb. Bit 13 bypasses
the first integrator/comb pair, bit 12 bypasses the second, etc. The first integrator is the largest. Typically, the stages are enabled
starting with stage 1 for maximum decimation range.
Carrier phase shift. Phase shifts of N*(π/4), N = 0 to 7. These bits remain for backward compatibility with the HSP50216. For new
designs, these bits should be set to 0 and the phase offset programmed into IWA *01CH.
Clear feedback (test signal or for mixer bypass).
NCO clear feedback on load.
Update frequency on SYNCI. Redundant. Set to1. See GWA register F802h.
Number of Carrier Offset Frequency (COF) serial input bits. The format is 2’s complement, early SYNC, MSB first:
00
8
01
16
10
24
11
32
Enable serial carrier offset frequency (zeros the data already loaded via the COF/COFSYNC pins). To disable the COF shifting see
IWA register *000h.
P(31:0)
31:0
TABLE 10. CARRIER NCO CENTER FREQUENCY REGISTER (IWA = *005h)
FUNCTION
Carrier Center Frequency (CCF):
This is the frequency control for the carrier NCO. The center frequency control is double buffered. The contents of this register are
transferred to the active register on a write to the CCF Strobe location or on a SYNCI (if load on SYNCI is enabled). The carrier center
frequency is: CCF*f_CLK/(2³²).
CCF is a twos complement number and has a range of -2³¹ to (2³¹-1). f_CLK is the input sample rate (ENIx assertion rate) for gated
mode and the clock rate for interpolated mode.
The value in the active register can be read at this address (the center frequency control before the serially loaded offset value is
added). To read the value, either write this address to A(1:0) = 11 and then read at A(1:0) = 00 and 01, or read the value at A(1:0) =
00 and 01 after writing to this address and before writing a new address to either A(1:0) = 10 or 11.
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