|
ISL5216 Datasheet, PDF (14/65 Pages) Intersil Corporation – Four-Channel Programmable Digital DownConverter | |||
|
◁ |
Filter Compute Engine
ISL5216
IQ
M
U
X
R/dÏ/dt
0..-23
INMUX (1:0)
I
Q
RAM
384
WORDS
I
Q
RAMR/Wb
ADDRA (8:0)
ADDRB (8:0)
0..-23
S
A
W
A
B
P
S
W
AA
P
B
DOWN SHIFT
1..-25
0, 1, 2 PLACES
WITH RND
1..-23
S
H 9..-31
F
T
R
E
G
0..-23
L
M
A
L
U
â
R
E
G
I
M
I
R
U
E
X
G
T
S
H
F
T
L
M
A
L
U
â
R
E
G
I
M
I
T
R
U
E
X
G
0..-21
COEF (21:0), SHIFT (1:0)
The ï¬lter compute engine is a dual multiply-accumulator
(MAC) data path with a microcoded FIR sequencer. The ï¬lter
compute engine can implement a single FIR or a set of
ï¬lters. For example, the ï¬lter chain could include two
halfband ï¬lters, a shaping (matched) ï¬lter and a resampling
ï¬lter, all with different decimations. The following ï¬lter types
are currently supported by the architecture and microcode:
⢠Even symmetric with even # of taps decimation ï¬lters
⢠Even symmetric with odd # of taps decimation ï¬lters
(including HBFs)
⢠Odd symmetric with even # of taps decimation ï¬lters
⢠Odd symmetric with odd # of taps decimation ï¬lters
⢠Asymmetric decimation ï¬lters
⢠Complex ï¬lters
⢠Interpolation ï¬lters (up to interpolate by 4)
⢠Interpolation halfband ï¬lters
⢠Resampling ï¬lters (under resampler NCO control)
⢠Fixed resampling ratio ï¬lter (within the available number of
coefï¬cients)
⢠Quadrature to real ï¬ltering (w/ fs/4 up conversion)
The input to the ï¬lter compute engine comes from one of
three sourcesâa CIC ï¬lter output (which can also be
another backend section), the output of the ï¬lter compute
engine (fed back to the input) or the magnitude and dÏ/dt fed
back from the cartesian-to-polar coordinate converter.
14
NOTE: PIPELINE DELAYS
OMITTED FOR CLARITY
The number and size of the ï¬lters in the chain is limited by the
number of clock cycles available (determined by the
decimation) and by the data and coefï¬cient RAM/ROM
resources. The data RAM is 384 words (I/Q pairs) deep. The
data addressing is modulo in power-of-2 blocks, so the
maximum ï¬lter size is 256. The block size and the block starting
memory address for each ï¬lter is programmable so that the
available memory can be used efï¬ciently. The coefï¬cient RAM
is 192 words deep. It is half the size of the data memory
because ï¬lter coefï¬cients are typically symmetric. ROMs are
provided with halfband ï¬lter coefï¬cients, resampling ï¬lter
coefï¬cients, and constants. The ï¬lter compute engine exploits
symmetry where possible so that each MAC can compute two
ï¬lter taps per clock by doing a pre-add before multiplying. In the
case of halfband ï¬lters, the zero-valued coefï¬cients are skipped
for extra efï¬ciency. There is an overhead of one clock cycle per
input sample for each ï¬lter in the chain (for writing the data into
the data RAM) and (except in special cases) a two clock cycle
overhead for the entire chain for program ï¬ow control
instructions.
The output of the ï¬lter compute engine is routed through a
FIFO in the main output path. The FIFO is provided to more
evenly space the FIR outputs when they are produced in bursts
(as when computing resampling or interpolation ï¬lters). The
FIFO is four samples deep. The FIFO is loaded by the output of
the ï¬lter when that path is selected. It is unloaded by a counter.
The spacing of the output samples is speciï¬ed in clock periods.
The spacing can be set from 1 (fall through) to 4096 samples
|
▷ |