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ISL5216 Datasheet, PDF (16/65 Pages) Intersil Corporation – Four-Channel Programmable Digital DownConverter | |||
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ISL5216
Sample ï¬lter #2 requires:
⢠32 + 32 + 128 + 8 = 200 data RAM locations
⢠(95+1)/2=48 coefï¬cient RAM location (resampler and HBF
coefï¬cients are in ROM).
The number of clock cycles required to compute an output
for Sample ï¬lter #2 is calculated as follows:
SAMPLE FILTER #2 CLOCK CYCLES CALCULATION
CLOCK
CYCLES
FUNCTION PERFORMED
20
Halfband 1 compute clocks
(5 per compute x 4 computes)
8
Halfband 1 input sample writes (8 input samples)
14
Halfband 2 compute clocks
(7 per compute x 2 computes)
4
Halfband 2 input sample writes (4 input samples)
48
95 tap symmetric FIR, 2 clocks per tap
2
FIR input sample writes (2 input samples)
6
Resampler (6 taps, nonsymmetric)
1
Resampler input sample write (1 input samples)
1
Jump instruction
1
Wait instruction
105 Clock cycles per output
Total decimation is 8, so the input sample rate for the FIR
chain (CIC output rate) could be up to:
fCLK/(ceil(105/8)) = fCLK/14.
With a 65MHz clock, this would support a maximum input
sample rate to the FIR processor of 4.6MHz and an output
sample rate up to 0.580MHz. The shaping ï¬lter impulse
response length would be:
(95 x 2)/580,000 = 82µs.
The maximum output sample rate is dependent on the
length and number of FIRs and their decimation factors.
Illustrating this concept with Filter Example #3, a higher
speed ï¬lter chain might be comprised of one 19 tap
decimate-by-2 halfband ï¬lter followed by a 30 tap shaping
FIR ï¬lter with no decimation. The program for this example
could be:
STEP
0
1
2
3
SAMPLE FILTER #3 PROGRAM
INSTRUCTION
Wait for enough input samples (2 in this case)
FIR
Type = even symmetry
19 taps
Halfband
Decimate by 2
Compute one output
Memory block size 32
Memory block start at 0
Coefficient block start at 18
Output to step 2
Reset wait count
FIR
Type = even symmetry
30 taps
Decimate by 1
Compute one output
Memory block size 64
Memory block start at 32
Coefficient block start at 64
Step size 1
Output to AGC
Jump, Unconditional, to 0
The number of clock cycles required to compute an output
for Sample ï¬lter #3 is calculated as follows:
SAMPLE FILTER #3 CLOCK CYCLES CALCULATION
CLOCK
CYCLES
FUNCTION PERFORMED
6
19 tap halfband, one output
2
halfband input writes (2 input samples)
15
30 tap symmetric FIR, 2 taps per clock
1
1 FIR input write
1
1 wait
1
1 jump
26
Clock cycles per output
For Filter Example #3 and a 65MSPS input, the maximum
FIR input rate would be 65MSPS / ceil(26 / 2) = 5MSPS
giving a decimate-by-2 output sample rate of 2.5MSPS. At
80MSPS, the FIR could have up to 42 taps with the same
output rate.
Channels 0, 1, 2 and 3 can be combined in a polyphase
structure for increased bandwidth or improved ï¬ltering.
Filter Example #4 will be used to demonstrate this capability.
Symbol rate of 4.096 MSym. The desired output sample rate
is 8.192MSPS. Arrange the four back end sections as four
ï¬lters operating on the same CIC output at a rate of
16
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