ISL5216 Datasheet, PDF (48/65 Pages) Intersil Corporation – Four-Channel Programmable Digital DownConverter

ISL5216
IRA
BITS
*003h
5:0
*004h
19:0
*005h
31:0
*007h
31:0
*008h
31:8
*00Ah
31:0
*00Bh
13:0
*00Ch
31:0
*00Dh
8:0
*00Eh
15:0
*00Fh
15:0
*010h
31:0
*011h
31:0
*012h
15:0
*013h
10:0
*014h
31:0
*015h
31:0
*016h
23:0
*017h
31:0
*018h
23:0
*01Ch
15:0
*100h - *17Fh 31:0
*180h - *1FCh 30:0
*400h - *43Fh 31:8
*440h - *47Fh 31:8
*480h - *4FFh 31:8
*500h - *5FFh 31:8
F800h
31:0
F801h
23:0
F802h
31:0
F803h
31:0
F804h
20:0
F805h
21:0
F806h
31:0
F807h
15:0
F80Bh
31:0
F820h - F83Fh 4:0
TABLE 50. TABLE OF INDIRECT READ ADDRESS (IRA) REGISTERS
FUNCTION
CIC Destination FIR and Output Enable/Disable
Carrier NCO / CIC Control
Active Carrier NCO Center Frequency.
Timing NCO Frequency (upper 32 bits)
Timing NCO Frequency (lower 24 bits)
Filter Compute Engine / Resampler Control
Filter Start Offset
Wait Threshold / Decrement Value
Reset Write Pointer Offset
AGC gain load register (reads gain initially loaded into AGC gain register)
AGC gain read (must first write to AGC gain read strobe register IWA = *00Fh before reading)
AGC Loop Attack / Decay Gain Values
AGC Gain Limits
AGC Threshold
AGC / Discriminator Control
Serial Data Output Control
Serial Data Output 1 Content / Format (Register 1)
Serial Data Output 1 Content / Format (Register 2)
Serial Data Output 2 Content / Format (Register 1)
Serial Data Output 2 Content / Format (Register 2)
Carrier Phase Offset
Instruction RAMs.
Instruction RAMs (pointer RAM).
Coefficient ROM -HBF, const.
Coefficient RAM -1.
Coefficient RAM -2.
Coefficient ROM -Resampler.
Test Control
Bus Routing Control
Reset / SYNC / Interrupt Source Selection
Serial Clock Control
Input Level Detector Source Select
Input Level Detector Configuration
Input Level Detector result (valid when bit 1 of status word is set)
µP / Test Input Bus
BIST
µP FIFO Read Order Control
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