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ISL5216 Datasheet, PDF (15/65 Pages) Intersil Corporation – Four-Channel Programmable Digital DownConverter | |||
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ISL5216
(approximately the spacing for a 16KSPS output sample rate
when using 65MSPS clock) using IWA = *00Ah bits 11:0.
The number and order of the ï¬ltering in the ï¬lter chain is
deï¬ned by a FIR control program. The FIR control program is a
sequence of up to 32 instruction words. Each instruction word
can be a ï¬lter or program ï¬ow instruction. The ï¬lter instruction
deï¬nes a FIR in the chain, specifying the type of FIR, number of
taps, decimation, memory allocation, etc. For program ï¬ow, a
wait for input sample(s) instruction, a loop counter load, and
several jumps (conditional and unconditional) are provided. The
ISL5216 evaluation board includes software for automatically
generating FIR control programs for most ï¬lter requirements.
Examples of programs FIR control programs are given below.
The simplest ï¬lter program computes a single ï¬lter. It has
three instructions (see Sample Filter #1 Program
Instructions below):
STEP
0
1
2
SAMPLE FILTER #1 PROGRAM
INSTRUCTION
Wait for enough input samples
(equal to the decimation factor)
FIR
Type = even symmetric
95 taps
Decimate by 2
Compute one output
Decrement wait counter
Memory block size 128
Memory block start at 64,
Coefficient block start at 64
Step size 1
Output to AGC
Jump, Unconditional, to step 0
The parameters of the FIR (including type, number of taps,
decimation and memory usage) are speciï¬ed in the bit ï¬elds
of the step 1 instruction word. To change the ï¬ltering the only
other change needed is the number of samples in the wait
threshold register (IWA = *00C, bits 9:0). The ï¬lter in this
example requires 52 clock cycles to compute, allocated as
follows:
SAMPLE FILTER #1 CLOCK CYCLES CALCULATION
CLOCK
CYCLES
FUNCTION PERFORMED
48
Clocks for FIR computation (two taps/clock due to
symmetry)
2
Clocks for writing the input data into the data RAMs
(Decimate by 2 requires 2 inputs per output)
2
Clocks for the program flow instructions (wait and
jump)
52
Total
Using a 65MSPS clock, the output sample rate could be as
high as 65MSPS / 52 clocks = 1.25MSPS. The input sample
rate to the FIR from the CIC ï¬lter would be 2.5MSPS. The
impulse response length would be 38µs (95 taps at
0.4µs/tap).
Each additional ï¬lter added to the signal processing chain
requires one instruction step. As an example of this, a typical
ï¬lter chain might consist of two decimate-by-2 halfband
ï¬lters being followed by a shaping ï¬lter with the ï¬nal ï¬lter
being a resampling ï¬lter. The program for this case might be
(see Sample Filter Program #2 Instructions below):
STEP
0
1
2
3
4
5
SAMPLE FILTER #2 PROGRAM
INSTRUCTION
Wait for enough input samples (usually equal to the
total decimationâ8 in this case)
FIR
Type = even symmetry
15 taps
Halfband
Decimate by 2
Compute four outputs
Memory block size 32
Memory block start at 0
Coefficient block start at 13
Output to step 2
Decrement wait count
FIR
Type = even symmetry
23 taps
Halfband
Decimate by 2
Compute two outputs
Memory block size 32
Memory block start at 32
Coefficient block start at 24
Output to step 3
FIR
Type = even symmetry
95 taps
Decimate by 2
Compute one output
Memory block size 128
Memory block start at 64
Coefficient block start at 64
Step size 1
Output to step 4
FIR
Type = resampler
Increment NCO
6 taps
Compute one output
Memory block size 8
Memory block starts at 192
Coefficient block start at 512
Step size 32
Output to AGC
Jump, Unconditional, to 0
15
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