ISL5216 Datasheet, PDF (50/65 Pages) Intersil Corporation – Four-Channel Programmable Digital DownConverter

ISL5216
Electrical Specifications V_CC1 = Core Supply: 2.5V ± 0.125V, V_CC2 = I/O Supply: 3.3 ± 0.165V ,
T_A = -40^oC to 85^oC Industrial
PARAMETER
SYMBOL
MIN
INPUT AND CONTROL TIMING (FIGURE 3)
CLK Frequency
CLK High (Note 25)
CLK Low (Note 25)
Setup Time - Data Inputs, Input Enables, SYNCI, SYNCI(0-3) to CLK High
Hold Time - Data Inputs, Input Enables, SYNCI, SYNCI(0-3) to CLK High
CLK to Output Valid - SYNCO, INTRPT
RESET Pulse Width Low
RESET Setup Time to CLK High (Note 24)
MICROPROCESSOR WRITE TIMING (µP MODE = 0, FIGURE 7)
f_CLK
-
t_CH
4.2
t_CL
4.2
t_DS
4
t_DH
-0.5
t_PDC
-
t_RW
5
t_RS
4
P(15:0) Setup Time to Rising Edge of WR
P(15:0) Hold Time from Rising Edge of WR
A(1:0) Setup Time to Rising Edge of WR
A(1:0) Hold Time from Rising Edge of WR
CE Setup Time to Rising Edge of WR
CE Hold Time from Rising Edge of WR
WR Low Time
WR High to CLK High (Note 25)
MICROPROCESSOR READ TIMING (µP MODE = 0, FIGURE 8)
t_PSW
7
t_PHW
-1
t_ASW
8
t_AHW
-1
t_CSW
8
t_CHW
-1
t_WL
5
t_WH
2
A(1:0) Hold Time from RISING Edge of RD (only applies when ADD(1:0) = 2)
A(1:0) to P(15:0) Data Valid Time
RD Low to P(15:0) Valid
RD Disable Time (Note 25)
CE to P(15:0) Data Valid Time
CE Hold Time from Rising Edge of RD (only applies when ADD(1:0) = 2)
RD Cycle Time for ADD(1:0) = 2 (Note 25)
MICROPROCESSOR WRITE TIMING (µP MODE = 1, FIGURE 9)
t_AHR
-2
t_DV
-
t_RE
-
t_RD
-
t_CSF
-
t_CHR
-2
t_RCY
16
P(15:0) Setup Time to Rising Edge of DSTRB
P(15:0) Hold Time from Rising Edge of DSTRB
A(1:0) Setup Time to Rising Edge of DSTRB
A(1:0) Hold Time from Rising Edge of DSTRB
CE Setup Time to Rising Edge of DSTRB
CE Hold Time from Rising Edge of DSTRB
R/W Setup Time to Falling Edge of DSTRB
R/W Hold Time from Rising Edge of DSTRB
DSTRB Low Time
DSTRB High to CLK High (Note 25)
MICROPROCESSOR READ TIMING (µP MODE = 1, FIGURE 10)
t_PSR
6
t_PHR
-1
t_ASR
8
t_AHR
-1
t_CSR
8
t_CHR
-1
t_R/WSF
1
t_R/WHR
0
t_DW
5
t_DSTH
2
A(1:0) Hold Time from RISING Edge of DSTRB (only applies when ADD(1:0) = 2)
A(1:0) to P(15:0) Data Valid Time
DSTRB Low to P(15:0) Valid
DSTRB Disable Time (Note 25)
CE to P(15:0) Data Valid Time
CE Hold Time from Rising Edge of DSTRB (only applies when ADD(1:0) = 2)
R/W Setup Time to Falling Edge of DSTRB
t_AHR
-1
t_DV
-
t_RE
-
t_RD
-
t_CSF
-
t_CHR
-1
t_R/WSF
1
50
MAX
95
-
-
-
-
6.5
-
-
-
-
-
-
-
-
-
-
-
16
11
7
16
-
-
-
-
-
-
-
-
-
-
-
-
16
11
7
16
-
-
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns