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| X80010 Datasheet, PDF (5/25 Pages) Intersil Corporation – Penta-Power Sequence Controller with Hot swap and System Management | |||
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X80010, X80011, X80012, X80013
Electrical Specifications (Standard Settings)
Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
tRESET_E Delay from PWRGD or ViGOOD to RESET
valid LOW
tQC
Delay from IGQ1 and IGQ0 to valid Gate pin
current
tSC_RETRY Delay between Retries
85
tNF
Noise Filter for Overcurrent
4.5
tDPOR Device Delay before Gate assertion
45
tSPOR Delay after PWRGD and all ViGOOD signals
85
are active before RESET assertion
tDELAY1 Power Sequencing Time Delay
85
tDELAY2 TiD1 = 0; TiD0 = 0
tDELAY3
tDELAY4
tTO
tPDHLPG(1)
tPDLHPG(1)
tPGHLPG(1)
tPGLHPG(1)
ViGOOD turn off time
Delay from Drain good to PWRGD LOW
Delay from Drain fail to PWRGD HIGH
Delay from Gate good to PWRGD LOW
Delay from Gate fail to PWRGD HIGH
Gate = VDD
Gate = VDD
Drain = VEE
Drain = VEE
NOTE:
1. This parameter is based on characterization data.
Equivalent A.C. Output Load Circuit
5V
5V
RESET
FAR
PWRGD
4.6kâ¦
30pF
V1GOOD,
V2GOOD,
V3GOOD,
V4GOOD
4.6kâ¦
30pF
TYP
MAX
UNIT
1
µs
1
µs
100
115
ms
5
5.5
µs
50
55
ms
100
115
ms
100
115
ms
50
ns
1
µs
1
µs
1
µs
1
µs
A.C. Test Conditions
Input pulse levels
Input rise and fall times
Input and output timing levels
Output load
VCC x 0.1 to VCC x 0.9
10ns
VCC x 0.5
Standard output load
5
FN8149.0
January 13, 2005
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