X80010 Datasheet, PDF (22/25 Pages) Intersil Corporation – Penta-Power Sequence Controller with Hot swap and System Management

Main FET
turns ON
EN1
(from PWRGD)
t_DELAY1
V1GDO
Power Supply
#1 OUTPUT
(3.3V)
EN2
(from PWRGD)
t_DELAY2
V2GDO
Power Supply
#2 OUTPUT
(2.5V)
100ms
X80010, X80011, X80012, X80013
the X80010 EN1 input to sequence the next supply. An
opto-coupler is recommended in this connection for
isolation. This configuration ensures that each
subsequent DC/DC supply will power up after the
preceding DC/DC supply voltage output is valid.
Power Supply
#1 turns ON
100ms
Power Supply
#2 turns ON
EN3
(from PWRGD)
t_DELAY3
V3GDO
Power Supply
#3 OUTPUT
(1.8V)
EN4
(from PWRGD)
t_DELAY4
V4GDO
Power Supply
#4 OUTPUT
(1.2V)
t_SPOR
100ms
Power Supply
#3 turns ON
100ms
Power Supply
#4 turns ON
100ms
RESET
All ViGOOD=LOW
FIGURE 42. PARALLEL SEQUENCING OF DC/DC SUPPLIES.
(TIMING)
1. Power Up of DC/DC Supplies Via Relay Sequencing
Using Power Good and Voltage Monitors (see Figure 43
and Figure 44).
Several DC/DC power supplies and their respective
power up start times can be controlled using the X80010
such that each of the DC/DC power supplies will start in
a relay sequencing fashion. The 1st DC/DC supply will
power up when PWRGD is LOW after a 100ms delay.
Subsequent DC/DC supplies will power up after the prior
supply has reached its operating voltage. One way to do
this is by using an external CPU Supervisor (for example
the Intersil X40430) to monitor the DC/DC output. When
the DC/DC voltage is good, the supervisor output signals
22
FN8149.0
January 13, 2005