X80010 Datasheet, PDF (18/25 Pages) Intersil Corporation – Penta-Power Sequence Controller with Hot swap and System Management

X80010, X80011, X80012, X80013
With the X80010, there is some control of the gate current
with the IGQ pins, so one selection of C2 can cover a wide
range of possible loading conditions. Typical values for C2
range from 2.2 to 4.7nF.
When power is applied to the system, the FET tries to turn
on due to its internal gate to drain capacitance (Cgd) and the
feedback capacitor C2 (see Figure 37.) The X80010 device,
when powered, pulls the gate output low to prevent the gate
voltage from rising and keep the FET from turning on.
However, unless V_DD powers up very quickly, there will be a
brief period of time during initial application of power when
the X80010 circuits cannot hold the gate low. The use of an
external capacitor (C1) prevents this. Capacitors C1 and C2
form a voltage divider to prevent the gate voltage from rising
above the FET turn on threshold before the X80010 can hold
the gate low. Use the following formula for choosing C1.
C1 = ^{V-----1-----–}----V-----2-- C2
V2
Where:
V1 = Maximum input voltage,
V2 = FET threshold voltage,
C1 = Gate capacitor,
C2 = Feedback capacitor.
In a system where V_DD rises very fast, a smaller value of C1
may suffice as the X80010 will control voltage at the gate
before the voltage can rise to the FET turn on threshold. The
circuit of Figure 37 assumes that the input voltage can rise to
80V before the X80010 sees operational voltage on V_DD. If
C1 is used then the series resistor R1 will be required to
prevent high frequency oscillations.
Drain Sense and Power Good Indicator
The X80010 provides a drain sense and power good
indicator circuit. The PWRGD signal asserts LOW when
there is no overvoltage, no undervoltage, and no overcurrent
condition, the Gate voltage exceeds VDD-1V, and the
voltage at the DRAIN pin is less V_EE+V_DRAIN.
As shown in Figure 38, this circuit block contains a drain
sense voltage trip point (∆V_DRAIN) and a gate voltage trip
point (∆V_GATE), two comparators, and internal voltage
references. These provide both a drain sense and a gate
sense circuit to determine the whether the FET has turned
on as requested. If so, the power good indicator (PWRGD)
goes active.
The drain sense circuit checks the DRAIN pin. If the voltage
on this pin is greater that 1V above V_EE, then a fault
condition exists.
The gate sense circuit checks the GATE pin. If the voltage
on this pin is less than V_EE - 1V, then a fault condition exists.
The PWRGD signal asserts (Logic LOW) only when all of the
below conditions are true:
- there is no overvoltage or no undervoltage condition,
(i.e. undervoltage < V_EE < overvoltage.)
- There is no overcurrent condition (i.e. V_EE - V_SENSE <
V_OC.)
- The FET is turned on (i.e. V_DRAIN < V_EE + 1V and
V_GATE > V_DD - 1V).
– ^∆VDRAIN
+
1V
(Factory
Programmable)
– ^∆VGATE
+ _VDD-1V
Power
Good
Logic
PWRGD
V_EE
Control/Status
Registers
V_EE SENSE GATE
DRAIN
100K
-48V
R_SENSE
LOAD
FIGURE 38. DRAIN SENSE AND POWER GOOD INDICATOR
Power On/System Reset and Delay
Application of power to the X80010 activates a Power On
Reset circuit that pulls the RESET pin active. This signal, if
used, provides several benefits.
- It prevents the system microprocessor from starting to
operate with insufficient voltage.
- It prevents the processor from operating prior to
stabilization of the oscillator.
- It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
The POR/RESET circuit is activated when all voltages are
within specified ranges and the following time-out conditions
are met: PWRGD and V1GOOD, V2GOOD, V3GOOD, and
V4GOOD. The POR/RESET circuit will then wait 100ms and
assert the RESET pin.
18
FN8149.0
January 13, 2005