X80010 Datasheet, PDF (17/25 Pages) Intersil Corporation – Penta-Power Sequence Controller with Hot swap and System Management

X80010, X80011, X80012, X80013
Hardshort Protection - FET Turn-on Retry
In the event on an over-current or hard short condition, the
X80010 includes a retry circuit. This circuit waits for 100ms,
then attempts to again turn on the FET. If the fault condition
still exists, the FET turns off and the sequence repeats. For
the X80010 and X80012, this process continues indefinitely
until the overcurrent condition does not exist. For the X80011
and X80013, this process repeats five times, only then will
keep the FET off and set the FAR pin active. After FAR is
asserted, it can be cleared using the master reset pin, MRH
(upon MRH assertion the FAR output is cleared) or cycling
the power on V_DD.
If an overcurrent condition does not occur on any retry, the
gate pin proceeds to open at the user defined slew rate.
Gate Drive Output Slew Rate (Inrush Current)
Control
The gate output drives an external N-Channel FET. The
GATE pin goes high when no overcurrent, undervoltage or
overvoltage conditions exist.
The X80010 provides an I_GATE current of 50µA to provide
on-chip slew rate control to minimize inrush current. This
I_GATE current limits the inrush current and provides the best
charge time for a given load, while avoiding overcurrent
conditions.
For applications that require different ramp rates during
insertion and start-up and operations modes, the X80010
provides two external pins, IGQ1 and IGQ0, that allow the
user to switch to different GATE currents on-the-fly by
selecting one of four pre-selected I_GATE currents. When
IGQ0 and IGQ1 are left unconnected, the gate current is
50µA. The other three settings are 10µA, 70µA and 150µA
(See Figure 36). Typically, the delay from IGQ1 and IGQ0
selection to a change in the GATE pin current is less than
1µs.
I_GATE =150µA
70µA
50µA
overcurrent
I_GATE
10µA
T1 T2 T3 T4 T5
Time, ms
FIGURE 36. SELECTING I_GATE CURRENT FOR SLEW RATE
CONTROL ON THE GATE PIN
Slew Rate (Gate) Control
As shown in Figure 37, this circuit block contains a current
source (I_GATE) that drives the 50µA current into the GATE
pin. This current provides a controlled slew rate for the FET.
For applications that require different ramp rates during
insertion and operation or for applications where a different
gate current is desired, the X80010 provides two external
pins, IGQ1 and IGQ0, that allow the system to switch to a
different GATE current with pre-selected options.
The IGQ1 and IGQ0 pins can be used to select from one of
four set values.
IGQ1 IGQ0
PIN PIN
CONTENTS
0
0 Defaults to gate current 50µA
0
1 Gate Current is 10µA
1
0 Gate Current is 70µA
1
1 Gate Current is 150µA
Typically, the delay from IGQ1 and IGQ0 selection to a
change in the GATE pin current is less than 1µs.
V_DD=12V
10µA
50µA
70µA
150µA
Slew
Rate
Selection
Logic
Gate Current
Quick Select
Logic
Control
Registers
IGQ1
IGQ0
V_EE SENSE GATE DRAIN
100nF*
100*
R2
22K
C2
3.3nF
100K
-48V
R_SENSE
I_INRUSH
LOAD
* Optional Components
See Section “Gate Capacitor, Filtering and Feedback”
FIGURE 37. SLEW RATE (INRUSH CURRENT) CONTROL
Gate Capacitor, Filtering and Feedback
In Figure 37, the FET control circuit includes an FET
feedback capacitor C₂, which provides compensation for the
FET during turn on. The capacitor value depends on the
load, the FET gate current, and the maximum desired inrush
current.
The value of C2 can be selected with the following formula.
C2 = ^I--G-----^A----^T---^E-----^×-----C-----^L---^O-----^A---^D---
I_INRUSH
Where:
I_GATE = FET Gate current
I_INRUSH = Maximum desired inrush current
C_LOAD = DC/DC bulk capacitance
17
FN8149.0
January 13, 2005