X80010 Datasheet, PDF (19/25 Pages) Intersil Corporation – Penta-Power Sequence Controller with Hot swap and System Management

X80010, X80011, X80012, X80013
Drain Sense
& Power
Good Logic
Enable
Logic
PWRGD
ViGOOD
i = 1 to 4
V_DD
SPOR
RESET
µP
RESET Logic
t_SPOR Delay
V_EE
MRC
Control
Registers
Once the PWRGD signal is asserted, the power sequencing
of the DC/DC modules can commence. RESET goes active
100ms after all ViGOOD (i=1 to 4) outputs are asserted (See
Figure 39).
As shown in Figure 40, this circuit block contains four
separate voltage enable pins, a time delay circuit, and an
output driver.
FIGURE 39. POWER ON/SYSTEM RESET AND DELAY
Quad Voltage Monitoring
X80010 monitors 4 voltage enable inputs. When the ENi
(i=1-4) input is detected to be below the input threshold, the
output ViGOOD (i = 1 to 4) goes active LOW. The ViGOOD
signal is asserted after a delay of 100ms. The ViGOOD
signal remains active until ENi rises above threshold.
EN1
EN2
EN3
EN4
V_RGO
OSC
Divider
Control Register
Reset
4
4
Select
0.1s
0.5s
1s
5s
delay1
delay2
delay3
delay4
Delay circuit
repeated 4 times
V_EE
FIGURE 40. VOLTAGE MONITORS AND VGOOD OUTPUTS
V1GOOD
V2GOOD
V3GOOD
V4GOOD
19
FN8149.0
January 13, 2005