X80010 Datasheet, PDF (15/25 Pages) Intersil Corporation – Penta-Power Sequence Controller with Hot swap and System Management

X80010, X80011, X80012, X80013
BATT-ON pin is pulled to V_RGO. The default thresholds have
been set so the external resistance values in Figure 30
provide an overvoltage threshold of 74.9V (X80010/X80012)
or 68V (X80011/X80013), a main undervoltage threshold of
43V and a battery undervoltage threshold of 33.8V.
As shown in Figure 34, this circuit block contains
comparators and voltage references to monitor for a single
overvoltage and dual undervoltage trip points. The
overvoltage and undervoltage trip points as shown in Table 1.
TABLE 1. OVERVOLTAGE/UNDERVOLTAGE DEFAULT
THRESHOLDS
THRESHOLD
MAX/MIN LOCKOUT
SYMBOL DESCRIPTION FALLING RISING VOLTAGE¹ VOLTAGE²
V_OV Overvoltage 3.87V 3.9V 74.3
(X80010/12)
74.9
V_OV Overvoltage 3.51V 3.54V 67.4
68
(X80011/13)
V_UV1 Undervoltage 1 2.21V 2.24V 43.0
42.4
V_UV2 Undervoltage 2 1.73V 1.76V 33.8
33.2
Notes: 1: Max/Min Voltage is the maximum and minimum operat-
ing voltage assuming the recommended V_UV/OV resis-
tor divider.
2: Lockout voltage is the voltage where the X8001x turns
off the FET.
A resistor divider connected between the plus and minus
input voltages and the V_UV/OV pin (see Figure 32)
determines the overvoltage and undervoltage shutdown
voltages and the operating voltage range. Using the
thresholds in Table and the equations of Figure 32 the
desired operating voltage can be determined. Figure 33
shows the resistance values for various operating voltages
(X80010 and X80012).
V_P
R1
Voltage divider:
V_{UV ⁄ OV}
=
V_S


R^-----1^---R--+^---2--R^-----2^{--}
V_S
V_UV/OV
or:
R2
V_N
V_S
=
V_UV
⁄
O
V


R_-----1_---R--+_---2--R_-----2_{--}
FIGURE 32. OVERVOLTAGE UNDERVOLTAGE DIVIDER
100
90
80
70 ^VOV
60
50 _VUV1
40
30
20 ^VUV2
10
0
BATT-ON = V_EE
Operating
Voltage
BATT-ON = V_RGO
R1 in kΩ (for R2=10K)
FIGURE 33. OPERATING VOLTAGe vs RESISTOR RATIO
Battery Back Up Operations
An external signal, BATT_ON is provided to switch the
undervoltage trip point. The BATT_ON signal is a LOGIC
HIGH if V_IHB > V_EE + 4V and is a LOGIC LOW if V_ILB < V_EE
+ 2V. The time from a BATT_ON input change to a valid new
undervoltage threshold is 100ns. See Electrical
Specifications for more details.
Note: The V_UV/OV pin must be limited to less than V_EE +
5.5V in worst case conditions. Values for R1 and R2 must be
chosen such that this condition is met. Intersil recommends
R1 = 182kΩ and R2 = 10kΩ to conform to factory settings.
TABLE 2. SELECTING BETWEEN UNDERVOLTAGE TRIP
POINTS
PIN
DESCRIPTION
TRIP POINT SELECTION
BATT_ON
Undervoltage Trip
Point
Selection Pin
If BATT_ON = 0,
V_UV1 trip point is selected;
If BATT_ON = 1,
V_UV2 trip point is selected.
V_UV1 and V_UV2 are undervoltage thresholds.
R1
182K
V_UV/OV
R2
10K
-48V
BATT_ON
-
+
V_{OV Voltage}
Reference
-
+
V_{UV1 Voltage}
Reference
-
+
V_{UV2 Voltage}
Reference
To Gate
Control
To Gate
Control
2:1
Mux
FIGURE 34. OVERVOLTAGE UNDERVOLTAGE FOR PRIMARY
AND BATTERY BACKUP
15
FN8149.0
January 13, 2005